Abstract: This specification relates to performance of partial store operation in a hierarchical memory system which has a buffer store interposed between a processor interrogating the memory system and the main memory of the memory system. Such a partial store operation can be performed on a word of data in the main memory using the buffer store copy of that word of data. The copy of the word of data is read out of the buffer store into a register where it is modified to form a new word by replacing one or more but not all of the bytes in the word of data with bytes supplied by the processor. The new word is then placed in the main memory by performing a full store operation. The problem with performing a partial store operation in this manner is that the copy of the word of data in the buffer store may not be up-to-date. A technique is provided to eliminate the possibility of this old data being rewritten back into the main memory.

Abstract: The disclosure describes a floating-priority storage access control arrangement for plural processors to a shared main storage in a multi-processing (MP) system. The shared main storage logically couples the main storage units provided with each of the processors into a single expanse of real addresses available to each processor. Exclusive access to the shared storage is given to any processor for as long as that processor can provide a burst of one or more successive storage requests. The burst ends when that processor misses a storage cycle by not providing a locally granted request.The shared storage access is controlled in each processor by means of an MP priority pointer circuit which receives storage requests granted by a local priority circuit in the processor. The MP priority pointer circuits are interconnected between the processors.