Patents by Inventor Dale M. Wong

Dale M. Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5359538
    Abstract: In a method for placement of components for a VLSI circuit, control signal connection networks and data signal connection networks are identified. Then, an initial placement of the components for the VLSI circuit is made. This initial placement is iteratively improved. The algorithm used for the iterative improvement has a cost metric in which a horizontal component for length of a connection network and a vertical component for length of the connection network are weighted differently dependent on whether the connection network was identified as a control signal connection network or a data signal connection network. The different weighting results in improved regularity of the placement of data path components and thus a more efficient routing of connection networks between the components.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: October 25, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Siu-Tong Hui, Dale M. Wong
  • Patent number: 5349536
    Abstract: In a method for placement of components for a VLSI circuit, an initial number of current placements are selected. A greedy optimization is partially performed on each of the current placements. Then, a subset of the current placements which have been partially optimized is selected to be the new current placements. This selection is based on a global cost metric for the current placements. The global cost metric is, for example, based on the total length of all connection line networks for the circuit. The partial optimization and selection are repeated until there is only one current placement. Then, an optimization is performed on the remaining placement to obtain an optimized placement. The optimization is, for example, a completion of the partially performed greedy optimization.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: September 20, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Sunil V. Ashtaputre, Dale M. Wong
  • Patent number: 5309370
    Abstract: Inter-area connectors are optimally placed on peripheries of bounded areas within an integrated circuit. Once circuit components are placed upon the integrated circuit, global optimum paths for connector lines between signal connectors within all the circuit components are calculated. This may be performed by calculating a global optimum rectilinear spanning tree for each net of signal connectors. Once the global optimum paths are calculated, inter-area connectors are placed at each location on a periphery of any of the circuit components where a global optimum path crosses the periphery. Finally, connector lines may be placed along the global optimum paths. For signal connectors and inter-area connectors within each circuit component, internal connector lines are routed between signal connectors along the global optimum paths within the circuit component. Also, between the circuit components, inter-area connector lines are routed between inter-area connectors along the global optimum paths.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: May 3, 1994
    Assignee: VLSI Technology, Inc.
    Inventor: Dale M. Wong
  • Patent number: 5208759
    Abstract: In a method for optimizing placement of circuit components on at least one integrated circuit, a list of circuit components is constructed. For each pairing of circuit components on the list, a total cost of the pairing is calculated. The total cost being calculated by first calculating the dead space resulting from the pairing, then estimating the total increase in routing area resulting from the pairing, and finally adding the dead space to the total increase in routing area to obtain the total cost. The estimation of the total increase in routing area resulting from the pairing is done by first estimating an increase in connectivity area resulting from the pairing. Then, a decrease in connectivity area resulting from the pairing is estimated. Finally, the decrease in connectivity area is subtracted from the increase in connectivity area to obtain the total increase in routing area.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: May 4, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Dale M. Wong
  • Patent number: 5202840
    Abstract: In a method for partitioning components of an integrated circuit into clusters in preparation for placement of the clusters onto an integrated circuit, a connectivity cost is assigned to every pair of connected components. Then, beginning with a pair of connected components with a lowest assigned connectivity cost and proceeding to a pair of connected components with a highest assigned connectivity cost, the components are placed in a cluster tree so that when merging cluster tree nodes, a cluster tree node with a higher connectivity cost is made a parent cluster tree node of a cluster tree node with a lower connectivity cost. The cluster tree may then traversed to partition the components into clusters. The clusters can be optimized by moving individual components to clusters when such a move results in a lower incremental connectivity cost. Once the components have been partitioned into clusters, the clusters of components may be placed on an integrated circuit.
    Type: Grant
    Filed: December 19, 1990
    Date of Patent: April 13, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Dale M. Wong
  • Patent number: 5187864
    Abstract: A method performs global routing of a power line network and a ground line network on an integrated circuit. Pre-formed segments of the ground line network are placed adjacent to functional blocks of the integrated circuit. Ground lines of the functional blocks are connected to the pre-formed segments of the ground line network. In addition, pre-formed segments of the power line network are placed adjacent to the functional blocks of the integrated circuit. Power lines of the functional blocks are connected to the pre-formed segments of the power line network. Once the pre-formed segments have all been placed, the pre-formed segments of the ground line network are connected together and the pre-formed segments of the power line network are connected together.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: February 23, 1993
    Assignee: VLSI Technology, Inc.
    Inventors: Daniel R. Brasen, Dale M. Wong