Abstract: A system includes a platform and a contactor. The platform has a side configured to support a frame with a carrier structure and electronic devices each having first and second sides and a terminal, the first side positioned on the carrier structure, and the terminal exposed in a first portion of the second side. The contactor has first and second sides, a contact and a heater. The contact is exposed on the first side of the contactor to contact the terminal in a first portion of the second side of a selected one of the electronic devices, and the heater is exposed on the first side of the contactor to apply heat to a second portion of the second side of the selected one of the electronic devices.

Abstract: A system includes a platform and a contactor. The platform has a side configured to support a frame with a carrier structure and electronic devices each having first and second sides and a terminal, the first side positioned on the carrier structure, and the terminal exposed in a first portion of the second side. The contactor has first and second sides, a contact and a heater. The contact is exposed on the first side of the contactor to contact the terminal in a first portion of the second side of a selected one of the electronic devices, and the heater is exposed on the first side of the contactor to apply heat to a second portion of the second side of the selected one of the electronic devices.

Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.

Abstract: Embodiments of the invention provide a semiconductor wafer with information for detecting a die attach pick error on the semiconductor wafer. The semiconductor wafer has a plurality of electrical chips. The semiconductor wafer also has a die map with a plurality of locations of a set of pre-selected check good electrical chips (CGEC) die from the plurality of electrical chips on the semiconductor wafer and flat edge orientation marker. A reference feature located in a predetermined area of the semiconductor wafer. A reference die is located in a known spatial relationship to the reference feature. The die map is defined relative to the location of the reference die on the semiconductor wafer.

Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.

Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.