Patents by Inventor Dale Ventura

Dale Ventura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus of ATE IC scan test using FPGA-based system
    Patent number: 8127187
    Abstract: An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing each of the plurality of devices, and providing test results to the ATE. The method comprises mounting a plurality of devices to be tested on the test load board, using the daughter card to communicate with the test board and the ATE, and using the daughter card for testing each of the plurality of DUTs, providing test results to the ATE. Also provided is a system to perform automated tests of integrated chips, comprising an ATE scan test unit, an off-load tester resource coupled to the ATE scan test unit, a processor executing commands to control the ATE unit and the off-load tester resource.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: February 28, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Yu Xia, Dale Ventura, Ashok Ramachandran
  • Method and Apparatus of ATE IC Scan Test Using FPGA-Based System
    Publication number: 20110078525
    Abstract: An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing each of the plurality of devices, and providing test results to the ATE. The method comprises mounting a plurality of devices to be tested on the test load board, using the daughter card to communicate with the test board and the ATE, and using the daughter card for testing each of the plurality of DUTs, providing test results to the ATE. Also provided is a system to perform automated tests of integrated chips, comprising an ATE scan test unit, an off-load tester resource coupled to the ATE scan test unit, a processor executing commands to control the ATE unit and the off-load tester resource.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Yu XIA, Dale Ventura, Ashok Ramachandran