Patents by Inventor Dales Kent

Dales Kent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9627281
    Abstract: A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: April 18, 2017
    Assignees: Advanced Micro Device, Inc., ATI Technologies ULC
    Inventors: Seth Prejean, Dales Kent, Ronnie Brandon, Gamal Refai-Ahmed, Michael Z. Su, Michael Bienek, Joseph Siegel, Bryan Black
  • Publication number: 20120043539
    Abstract: A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Inventors: Seth Prejean, Dales Kent, Ronnie Brandon, Gamal Refai-Ahmed, Michael Z. Su, Michael Bienek, Joseph Siegel, Bryan Black
  • Patent number: 7652572
    Abstract: Methods for detecting and locating ferromagnetic objects in a security screening system. One method includes a step of acquiring magnetic data that includes magnetic field gradients detected during a period of time. Another step includes representing the magnetic data as a function of the period of time. Another step includes converting the magnetic data to being represented as a function of frequency. Another method includes a step of sensing a magnetic field for a period of time. Another step includes detecting a gradient within the magnetic field during the period of time. Another step includes identifying a peak value of the gradient detected during the period of time. Another step includes identifying a portion of time within the period of time that represents when the peak value occurs. Another step includes configuring the portion of time over the period of time to represent a ratio.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: January 26, 2010
    Assignee: Battelle Energy Alliance, LLC
    Inventors: Lyle Gene Roybal, Dale Kent Kotter, David Thomas Rohrbaugh, David Frazer Spencer
  • Patent number: 7421576
    Abstract: Methods and systems in a data/computer network for authenticating identifying data transmitted from a client to a server through use of a gateway interface system which are communicately coupled to each other are disclosed. An authentication packet transmitted from a client to a server of the data network is intercepted by the interface, wherein the authentication packet is encrypted with a one-time password for transmission from the client to the server. The one-time password associated with the authentication packet can be verified utilizing a one-time password token system. The authentication packet can then be modified for acceptance by the server, wherein the response packet generated by the server is thereafter intercepted, verified and modified for transmission back to the client in a similar but reverse process.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: September 2, 2008
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: Alexander Dale Kent
  • Publication number: 20080084301
    Abstract: Methods for detecting and locating ferromagnetic objects in a security screening system. One method includes a step of acquiring magnetic data that includes magnetic field gradients detected during a period of time. Another step includes representing the magnetic data as a function of the period of time. Another step includes converting the magnetic data to being represented as a function of frequency. Another method includes a step of sensing a magnetic field for a period of time. Another step includes detecting a gradient within the magnetic field during the period of time. Another step includes identifying a peak value of the gradient detected during the period of time. Another step includes identifying a portion of time within the period of time that represents when the peak value occurs. Another step includes configuring the portion of time over the period of time to represent a ratio.
    Type: Application
    Filed: October 9, 2006
    Publication date: April 10, 2008
    Inventors: Lyle Gene Roybal, Dale Kent Kotter, David Thomas Rohrbaugh, David Frazer Spencer
  • Publication number: 20070210819
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 13, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205757
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205797
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205786
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205773
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205758
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205756
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205796
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20060152237
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: January 12, 2005
    Publication date: July 13, 2006
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20050280140
    Abstract: In an integrated circuit packaging structure, such as in a SCM, DCM, or MCM, a method and apparatus for increasing heat spreader size and thus thermal performance is disclosed. The packaging structure includes a first substrate; an electronic device operably coupled to a top surface defining the first substrate; a heat spreader having a first surface operably coupled to a top surface defining the electronic device and an opposite second surface in thermal communication with a second substrate; and a frame defining an opening therethrough. The frame is further defined by an inwardly extending ledge configured to allow the heat spreader to extend at least to a peripheral edge defining a perimeter of the first substrate. In an exemplary embodiment, the second substrate includes one of a heat sink, cooling plate, thermal spreader, heat pipe, thermal hat, package lid, or other cooling member.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 22, 2005
    Applicant: International Business Machines Corporation
    Inventors: John Corbin, Gary Goth, Dales Kent, William Kostenko, Roger Schmidt, John Torok
  • Publication number: 20050030053
    Abstract: An innovative chip testing system and method includes controlling temperature and condensation during testing. Coarse temperature is controlled by providing a desired fluid flow rate and fluid temperature to a cold plate. Fine temperature control is provided by a feedback loop which controls the power dissipation of cartridge heaters installed within the cold plate. Condensation control is provided by insulating various components of the system, manipulation of dry compressed air in enclosures to reduce surface dew point temperatures, usage of cartridge heaters in a card backside stiffener plate, and by providing a heatsink assembly which prevents condensation on the insulation.
    Type: Application
    Filed: August 20, 2004
    Publication date: February 10, 2005
    Inventors: Daniel Beaman, John Corbin, Dales Kent, Howard Mahaney, Hoa Phan, Frederic Wright
  • Publication number: 20050030052
    Abstract: An innovative chip testing system and method includes controlling temperature and condensation during testing. Coarse temperature is controlled by providing a desired fluid flow rate and fluid temperature to a cold plate. Fine temperature control is provided by a feedback loop which controls the power dissipation of cartridge heaters installed within the cold plate. Condensation control is provided by insulating various components of the system, manipulation of dry compressed air in enclosures to reduce surface dew point temperatures, usage of cartridge heaters in a card backside stiffener plate, and by providing a heatsink assembly which prevents condensation on the insulation.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 10, 2005
    Applicant: International Business Machines Corporation
    Inventors: Daniel Beaman, John Corbin, Dales Kent, Howard Mahaney, Hoa Phan, Frederic Wright