Abstract: Some embodiments include apparatuses comprising a first node; a second node; a first transistor and a second transistor, the first and second transistors including a common gate coupled to the node and a common terminal coupled to the second node; first additional transistors coupled in parallel with each other between a terminal of the first transistor and a first supply node, the first additional transistors including gates; and second additional transistors coupled in parallel with each other between a terminal of the second transistor and a second supply node, the second additional transistors including gates.

Abstract: Disclosed herein are embodiments of a scalable connection and disconnection differential surge limiter circuit that may be utilized in any AC-coupled transceiver. Charge is recycled between PADP and PADN using two diode paths, hence protecting the PAD connected devices from voltage stress. The circuit can act as a protection circuit to limit the voltage on PADP and PADN during differential voltage spikes.

Abstract: Disclosed herein are embodiments of a scalable connection and disconnection differential surge limiter circuit that may be utilized in any AC-coupled transceiver. Charge is recycled between PADP and PADN using two diode paths, hence protecting the PAD connected devices from voltage stress. The circuit can act as a protection circuit to limit the voltage on PADP and PADN during differential voltage spikes.

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract: An analog disconnection envelope detection circuit having a low power supply detects a high speed, high differential voltage disconnect state on a data line. Level-shifting circuitry shifts the voltage level of two input signals by the value of a detection threshold voltage, generates differential signals used to indicate conditions of the input signals, and mitigates effects of input differential signal common-mode voltage on the detection operation. Circuitry is provided to equalize VDS of detecting tail current sources, thereby eliminating errors resulting from VDS mismatch of tail current sources. Comparator circuitry compares the sets of differential signals and indicates when the absolute difference between the two input signals is greater than a reference voltage. Output circuitry generates a disconnect signal corresponding to the disconnect condition.

Abstract: An analog disconnection envelope detection circuit having a low power supply detects a high speed, high differential voltage disconnect state on a data line. Level-shifting circuitry shifts the voltage level of two input signals by the value of a detection threshold voltage, generates differential signals used to indicate conditions of the input signals, and mitigates effects of input differential signal common-mode voltage on the detection operation. Circuitry is provided to equalize VDS of detecting tail current sources, thereby eliminating errors resulting from VDS mismatch of tail current sources. Comparator circuitry compares the sets of differential signals and indicates when the absolute difference between the two input signals is greater than a reference voltage. Output circuitry generates a disconnect signal corresponding to the disconnect condition.

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract: An embodiment of an impedance calibration circuit and method, a device including an impedance calibration circuit, and a transmission link system.