Abstract: Fault tolerant operation of a microprocessor-based control system is provided by proper execution of an operating program stored in a read only memory (ROM) by a central processing unit (CPU), or microprocessor/microcomputer, as determined by monitoring program access of a select memory location within the ROM. Failure to access the select memory location within a designated time period indicates improper CPU operation and allows a shift register to output a reset signal to automatic reset circuitry for reinitializing CPU operation. The automatic reset circuitry monitors CPU operation and continually attempts to reset the CPU until proper resetting thereof is accomplished. A visual and/or aural indication of CPU reset as well as the number of times it is reset is provided to an operator. The CPU is coupled to a host computer for indicating to the host computer that the CPU has been reset and is now ready to receive data from the host computer.

Abstract: Recovery from loss of synchronization of a synchronous serial receiver is assured by automatic reset circuitry described herein. In a synchronous serial data receiver, synchronization, data and fill characters are received from a synchronous signal transmitter. The synchronization character is provided at the beginning of each data record to establish receiver synchronization before control data is received. The fill character is used to maintain synchronization during data reception when no useful data is available for transmission. Detection of either of these characters indicates receiver synchronization with the received data. Failure to detect either of these characters during a predetermined time interval is sensed as an error indicating that the receiver has lost synchronization with the received data.