Patents by Inventor Dalong Du

Dalong Du has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processing method and apparatus for single-channel convolution layer, and processing method and apparatus for multi-channel convolution layer
    Patent number: 9367892
    Abstract: A processing method and a processing apparatus for a single-channel convolution layer, and a processing method and apparatus for a multi-channel convolution layer are provided. The processing method for a single-channel convolution layer includes following steps. Data to be processed is divided into a plurality of data blocks, the plurality of data blocks are read by a plurality of graphic processor thread groups into local memories of the plurality of graphic processor thread groups, a plurality of filters are read by the plurality of graphic processor thread groups into the local memories of the plurality of graphic processor thread groups and convolutions of corresponding data points in the plurality of data blocks and the plurality of filters simultaneously are calculated by a plurality of threads in the plurality of graphic processor thread groups.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: June 14, 2016
    Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Ren Wu, Shigang Li, Dalong Du, Wenzhi Liu
  • PROCESSING METHOD AND APPARATUS FOR SINGLE-CHANNEL CONVOLUTION LAYER, AND PROCESSING METHOD AND APPARATUS FOR MULTI-CHANNEL CONVOLUTION LAYER
    Publication number: 20150371359
    Abstract: A processing method and a processing apparatus for a single-channel convolution layer, and a processing method and apparatus for a multi-channel convolution layer are provided. The processing method for a single-channel convolution layer includes following steps. Data to be processed is divided into a plurality of data blocks, the plurality of data blocks are read by a plurality of graphic processor thread groups into local memories of the plurality of graphic processor thread groups, a plurality of filters are read by the plurality of graphic processor thread groups into the local memories of the plurality of graphic processor thread groups and convolutions of corresponding data points in the plurality of data blocks and the plurality of filters simultaneously are calculated by a plurality of threads in the plurality of graphic processor thread groups.
    Type: Application
    Filed: December 22, 2014
    Publication date: December 24, 2015
    Inventors: Ren Wu, Shigang Li, Dalong Du, Wenzhi Liu