Patents by Inventor Damian A. Carver

Damian A. Carver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9012308
    Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Atmel Corporation
    Inventors: Darwin Gene Enicks, John Chaffee, Damian A. Carver
  • Publication number: 20140001603
    Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AtGaAs are also amenable to beneficial processes described herein.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 2, 2014
    Applicant: ATMEL CORPORATION
    Inventors: Darwin Gene Enicks, John Chaffee, Damian A. Carver
  • Patent number: 8530934
    Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: September 10, 2013
    Assignee: Atmel Corporation
    Inventors: Darwin G. Enicks, John Taylor Chaffee, Damian A. Carver
  • Publication number: 20110073907
    Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.
    Type: Application
    Filed: October 11, 2010
    Publication date: March 31, 2011
    Applicant: Atmel Corporation
    Inventors: Darwin G. Enicks, John Taylor Chaffee, Damian A. Carver
  • Patent number: 7408812
    Abstract: The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: August 5, 2008
    Assignee: Atmel Corporation
    Inventors: Muhammad I. Chaudhry, Damian A. Carver
  • Publication number: 20070148890
    Abstract: A method for pseudomorphic growth and integration of a strain-compensated metastable and/or unstable compound base having incorporated oxygen and an electronic device incorporating the base is described. The strain-compensated base is doped by substitutional and/or interstitial placement of a strain-compensating atomic species. The electronic device may be, for example, a SiGe NPN HBT.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 28, 2007
    Inventors: Darwin G. Enicks, John T. Chaffee, Damian A. Carver
  • Patent number: 7208795
    Abstract: An EEPROM memory transistor having a floating gate. The floating gate is formed using a BiCMOS process and has a first sinker dopant region proximate to a tunnel diode window, and a second sinker dopant region proximate to a coupling capacitor region. An optional third sinker region may be formed proximate to a source junction of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region may be formed between the first and second sinker dopant regions.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: April 24, 2007
    Assignee: Atmel Corporation
    Inventors: Damian A. Carver, Muhammad I. Chaudhry
  • Patent number: 7144775
    Abstract: The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: December 5, 2006
    Assignee: Atmel Corporation
    Inventors: Muhammad I. Chaudhry, Damian A. Carver