Abstract: Systems and methods for estimating power consumption in a network of computing devices are described. Operational information of a target server is periodically received and compared to benchmark data of a model of the target server. The operational information comprises performance data of the target server during a predefined time interval. Power consumption of the target server is estimated using the performance and benchmark data. The benchmark data is recalibrated if an error in the estimated power consumption is detected. An agent installed on the target server for collecting performance data is described. The target server can be a virtualized server, in which case, the agent acquires at least some of the performance data from a hypervisor of a physical server that hosts the target server.

Abstract: Systems and methods for estimating power consumption in a network of computing devices are described. Operational information of a target server is periodically received and compared to benchmark data of a model of the target server. The operational information comprises performance data of the target server during a predefined time interval. Power consumption of the target server is estimated using the performance and benchmark data. The benchmark data is recalibrated if an error in the estimated power consumption is detected. An agent installed on the target server for collecting performance data is described. The target server can be a virtualized server, in which case, the agent acquires at least some of the performance data from a hypervisor of a physical server that hosts the target server.

Abstract: A parallel processor for a logic event simulation (APPLES) including a main processor and an associative memory mechanism including a response resolver. Further, the associative memory mechanism includes a plurality of separate associative sub-registers each for storing in word form of a history of gate input signals for a specified type of logic gate, and a plurality of separate additional sub-registers associated with each associative sub-register whereby gate evaluations and tests can be carried out in parallel on each associative sub-register.

Abstract: A method and a processor for parallel processing of logic event simulation on circuits comprising a polarity of logic gates, the logic gates having interconnect lines therebetween, the processor (1) further comprising a main processor (2) and an associative memory mechanism (3), the associative memory mechanism (3) comprising a plurality of associative arrays (5, 6) and at least one result register, and there is provided accessible external memory (4) in which a circuit representation may be stored and divided into a plurality of segments, each of the segments having a segment identifier, which in turn has segment data associated therewith. The segment identifier and segment data being stored in a segment table (14) in the associative memory mechanism. Each of the segments may then be brought into the associative memory mechanism (3) for evaluation one at a time. There is additionally provided an amended result registering mechanism (8) to allow numerous tests and gate pairs to be carried out and recorded.