Patents by Inventor Damian Osisek

Damian Osisek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050289246
    Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 29, 2005
    Applicant: International Business Machines Corporation
    Inventors: Janet Easton, William Holder, Bernd Nerz, Damian Osisek, Gustav Sittmann, Richard Tarcza, Leslie Wyman
  • Publication number: 20050268071
    Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 1, 2005
    Applicant: International Business Machines Corporation
    Inventors: Geoffrey Blandy, Janet Easton, Lisa Heller, William Holder, Damian Osisek, Gustav Sittmann, Richard Tarcza, Leslie Wyman
  • Publication number: 20050114586
    Abstract: A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with a definition of a z/Architecture; allocating at least one of a real resource and a virtual resource associated with the first alternate address space to a process; ensuring that the selected process corresponds with the process to which the resource is allocated. The process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.
    Type: Application
    Filed: November 25, 2003
    Publication date: May 26, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frank Brice, Richard Errickson, Mark Farrell, Charles Gainey, Thomas Gregg, Carol Hernandez, Damian Osisek, Donald Schmidt