Abstract: A display controller for a data processing system comprises two sets of display processing units, each set of display processing units comprising an input unit operable to read at least one input surface, a processing unit operable to process one or more input surfaces to generate an output surface, and an output unit operable to provide an output surface for display to a display. The display controller also includes internal data path via which pixel data of a surface may be passed between the sets of display processing units, and a control unit that can selectively activate one or both of the sets of display processing units to process one or more input surfaces to generate one or more output surfaces for display.

Abstract: A display controller for a data processing system comprises two sets of display processing units, each set of display processing units comprising an input unit operable to read at least one input surface, a processing unit operable to process one or more input surfaces to generate an output surface, and an output unit operable to provide an output surface for display to a display. The display controller also includes internal data path via which pixel data of a surface may be passed between the sets of display processing units, and a control unit that can selectively activate one or both of the sets of display processing units to process one or more input surfaces to generate one or more output surfaces for display.

Abstract: A display controller 93 in a data processing system includes a timewarp module (transformation circuitry) 100 that is operable to perform timewarp processing of a rendered frame 92 generated by a graphics processor (GPU) 91 for provision to a display panel 94. The timewarp module (transformation circuitry) 100 operates to transform an input surface 92 read by the display controller 93 based on received view orientation data to provide an appropriately “timewarped” transformed version of the input surface as an output transformed surface for display on the display 94.

Abstract: An apparatus for compositing an output surface (10) from a plurality of input surfaces (1, 2, 3, 4) includes processing circuitry and a composition processor. The processing circuitry is configured to determine whether two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be combined into a single secondary surface for provision to the composition processor. When it is determined that two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be combined into a single secondary surface for provision to the composition processor, the processing circuitry is configured to provide data representing the secondary surface to the composition processor, the data indicating the input surfaces that contribute to the secondary surface.

Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller. The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.

Abstract: A display controller 10 comprises a first display processing core 20 comprising a first input stage operable to read at least one input surface, a first processing stage operable to generate an output surface, a first output stage operable to provide an output surface for display to a first display 3, and a first write-out stage 27 operable to write data of an output surface to external memory 1, and a second display processing core 40 comprising a second input stage operable to read at least one input surface, a second processing stage operable to generate an output surface, and a second output stage operable to provide an output surface for display to a second display 5. The display controller 10 also comprises an internal data path 30 for passing data of an output surface from the first display core 20 to the second display core 40.

Abstract: A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.