Patents by Inventor Damiana Lerose
Damiana Lerose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240053551Abstract: A wafer with a buried V-groove cavity, and a method for fabricating V-grooves. In some embodiments, the method includes bonding a first layer, to a top surface of a substrate, to form a composite wafer, the first layer being composed of a first semiconductor material, the substrate being composed of a second semiconductor material, the top surface of the substrate having a cavity, the cavity including a V-groove.Type: ApplicationFiled: December 10, 2021Publication date: February 15, 2024Inventors: Janne Ikonen, John Paul Drake, Henri Nykänen, Damiana Lerose
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Patent number: 11600532Abstract: A method for fabricating an integrated structure, using a fabrication system having a CMOS line and a photonics line, includes the steps of: in the photonics line, fabricating a first photonics component in a silicon wafer; transferring the wafer from the photonics line to the CMOS line; and in the CMOS line, fabricating a CMOS component in the silicon wafer. Additionally, a monolithic integrated structure includes a silicon wafer with a waveguide and a CMOS component formed therein, wherein the waveguide structure includes a ridge extending away from the upper surface of the silicon wafer. A monolithic integrated structure is also provided which has a photonics component and a CMOS component formed therein, the photonics component including a waveguide having a width of 0.5 ?m to 13 ?m.Type: GrantFiled: May 19, 2021Date of Patent: March 7, 2023Assignee: Rockley Photonics LimitedInventors: Aaron Zilkie, Andrew Rickman, Damiana Lerose
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Patent number: 11513292Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; andType: GrantFiled: May 4, 2020Date of Patent: November 29, 2022Inventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
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Publication number: 20210335677Abstract: A method for fabricating an integrated structure, using a fabrication system having a CMOS line and a photonics line, includes the steps of: in the photonics line, fabricating a first photonics component in a silicon wafer; transferring the wafer from the photonics line to the CMOS line; and in the CMOS line, fabricating a CMOS component in the silicon wafer. Additionally, a monolithic integrated structure includes a silicon wafer with a waveguide and a CMOS component formed therein, wherein the waveguide structure includes a ridge extending away from the upper surface of the silicon wafer. A monolithic integrated structure is also provided which has a photonics component and a CMOS component formed therein, the photonics component including a waveguide having a width of 0.5 ?m to 13 ?m.Type: ApplicationFiled: May 19, 2021Publication date: October 28, 2021Inventors: Aaron ZILKIE, Andrew RICKMAN, Damiana LEROSE
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Patent number: 11150494Abstract: A Mach-Zehnder waveguide modulator. In some embodiments, the Mach-Zehnder waveguide modulator includes a first arm including a first optical waveguide, and a second arm including a second optical waveguide. The first optical waveguide includes a junction, and the Mach-Zehnder waveguide modulator further includes a plurality of electrodes for providing a bias across the junction to enable control of the phase of light travelling through the junction.Type: GrantFiled: August 23, 2019Date of Patent: October 19, 2021Assignee: Rockley Photonics LimitedInventors: Guomin Yu, Hooman Abediasl, Aaron L. Birkbeck, Jeffrey Driscoll, Haydn Frederick Jones, Damiana Lerose, Amit Singh Nagra, David Arlo Nelson, Dong Yoon Oh, Pradeep Srinivasan, Aaron John Zilkie
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Patent number: 11133225Abstract: An optical fiber adapter and method of fabricating the same from a wafer including a double silicon-on-insulator layer structure. The optical fiber adapter may include a mode converter, a trench, and a V-groove, the V-groove and the trench operating as passive alignment features for an optical fiber, in the transverse translational and rotational degrees of freedom, and in the longitudinal translational degree of freedom, respectively. The mode converter may include a buried tapered waveguide.Type: GrantFiled: May 1, 2020Date of Patent: September 28, 2021Assignee: Rockley Photonics LimitedInventors: John Drake, Damiana Lerose, Henri Nykänen, Gerald Cois Byrd
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Patent number: 11105975Abstract: A waveguide optoelectronic device comprising a rib waveguide region, and method of manufacturing a rib waveguide region, the rib waveguide region having: a base of a first material, and a ridge extending from the base, at least a portion of the ridge being formed from a chosen semiconductor material which is different from the material of the base wherein the silicon base includes a first slab region at a first side of the ridge and a second slab region at a second side of the ridge; and wherein: a first doped region extends along: the first slab region and along a first sidewall of the ridge, the first sidewall contacting the first slab region; and a second doped region extends along: the second slab region and along a second sidewall of the ridge, the second sidewall contacting the second slab region.Type: GrantFiled: December 1, 2017Date of Patent: August 31, 2021Assignee: Rockley Photonics LimitedInventors: Hooman Abediasl, Damiana LeRose, Amit Singh Nagra, Guomin Yu
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Patent number: 11101256Abstract: An optoelectronic device. The optoelectronic device operable to provide a PAM-N modulated output, the device comprising: M optical modulators, M being an integer greater than 1, the M optical modulators being arranged in a cascade, the device being configured to operate in N distinct transmittance states, as a PAM-N modulator, wherein, in each transmittance state of the N distinct transmittance states, each of the M optical modulators has applied to it a respective control voltage equal to one of: a first voltage or a second voltage. One or more of the modulators may include a substrate; a crystalline cladding layer, on top of the substrate; and an optically active region, above the crystalline cladding layer. The crystalline cladding layer may have a refractive index which is less than a refractive index of the optically active region.Type: GrantFiled: November 19, 2018Date of Patent: August 24, 2021Assignee: Rockley Photonics LimitedInventors: Guomin Yu, Amit Singh Nagra, Damiana Lerose, Hooman Abediasl, Pradeep Srinivasan, Joyce Kai See Poon, Zheng Yong, Haydn Frederick Jones
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Patent number: 11037839Abstract: A method for fabricating an integrated structure, using a fabrication system having a CMOS line and a photonics line, includes the steps of: in the photonics line, fabricating a first photonics component in a silicon wafer; transferring the wafer from the photonics line to the CMOS line; and in the CMOS line, fabricating a CMOS component in the silicon wafer. Additionally, a monolithic integrated structure includes a silicon wafer with a waveguide and a CMOS component formed therein, wherein the waveguide structure includes a ridge extending away from the upper surface of the silicon wafer. A monolithic integrated structure is also provided which has a photonics component and a CMOS component formed therein, the photonics component including a waveguide having a width of 0.5 ?m to 13 ?m.Type: GrantFiled: July 13, 2017Date of Patent: June 15, 2021Assignee: Rockley Photonics LimitedInventors: Aaron Zilkie, Andrew Rickman, Damiana Lerose
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Patent number: 11036006Abstract: A waveguide device and method of doping a waveguide device, the waveguide device comprising a rib waveguide region, the rib waveguide region having: a base, and a ridge extending from the base, wherein: the base includes a first slab region at a first side of the ridge and a second slab region at a second side of the ridge; a first doped slab region extends along the first slab region; a second doped slab region extends along the second slab region; a first doped sidewall region extends along a first sidewall of the ridge and along a portion of the first slab, the first doped sidewall region being in contact with the first doped slab region at a first slab interface; and a second doped sidewall region extends along a second sidewall of the ridge and along a portion of the second slab, the second doped sidewall region being in contact with the second doped slab region at a second slab interface; and wherein the separation between the first sidewall of the ridge and the first slab interface is no more than 10 ?Type: GrantFiled: December 1, 2017Date of Patent: June 15, 2021Assignee: Rockley Photonics LimitedInventors: Damiana Lerose, Hooman Abediasl, Amit Singh Nagra
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Patent number: 10955692Abstract: An optoelectronic component including a waveguide, the waveguide comprising an optically active region (OAR), the OAR having an upper and a lower surface; a lower doped region, wherein the lower doped region is located at and/or adjacent to at least a portion of a lower surface of the OAR, and extends laterally outwards from the OAR in a first direction; an upper doped region, wherein the upper doped region is located at and/or adjacent to at least a portion of an upper surface of the OAR, and extends laterally outwards from the OAR in a second direction; and an intrinsic region located between the lower doped region and the upper doped region.Type: GrantFiled: November 10, 2016Date of Patent: March 23, 2021Assignee: Rockley Photonics LimitedInventors: Guomin Yu, Hooman Abediasl, Damiana Lerose, Kevin Masuda, Andrea Trita, Aaron Zilkie
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Patent number: 10928659Abstract: An optoelectronic device and method of making the same. The device comprising: a substrate; an epitaxial crystalline cladding layer, on top of the substrate; and an optically active region, above the epitaxial crystalline cladding layer; wherein the epitaxial crystalline cladding layer has a refractive index which is less than a refractive index of the optically active region, such that the optical power of the optoelectronic device is confined to the optically active region.Type: GrantFiled: February 13, 2019Date of Patent: February 23, 2021Assignee: Rockley Photonics LimitedInventors: Andrew Rickman, Aaron Zilkie, Guomin Yu, Hooman Abediasl, Damiana Lerose, Amit Singh Nagra, Pradeep Srinivasan, Haydn Jones
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Patent number: 10921616Abstract: An optoelectronic device and method of making the same. The device comprising: a substrate; an epitaxial crystalline cladding layer, on top of the substrate; and an optically active region, above the epitaxial crystalline cladding layer; wherein the epitaxial crystalline cladding layer has a refractive index which is less than a refractive index of the optically active region, such that the optical power of the optoelectronic device is confined to the optically active region.Type: GrantFiled: May 22, 2019Date of Patent: February 16, 2021Assignee: Rockley Photonics LimitedInventors: Guomin Yu, Hooman Abediasl, Damiana Lerose, Amit Singh Nagra, Pradeep Srinivasan, Haydn Jones
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Patent number: 10816830Abstract: An optoelectronic device and method of making the same. The device comprising: a substrate; an epitaxial crystalline cladding layer, on top of the substrate; and an optically active region, above the epitaxial crystalline cladding layer; wherein the epitaxial crystalline cladding layer has a refractive index which is less than a refractive index of the optically active region, such that the optical power of the optoelectronic device is confined to the optically active region.Type: GrantFiled: February 13, 2019Date of Patent: October 27, 2020Assignee: ROCKLEY PHOTONICS LIMITEDInventors: Andrew Rickman, Aaron Zilkie, Guomin Yu, Hooman Abediasl, Damiana Lerose, Amit Singh Nagra, Pradeep Srinivasan, Haydn Jones
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Publication number: 20200264372Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and aType: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
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Publication number: 20200258791Abstract: An optical fiber adapter and method of fabricating the same from a wafer including a double silicon-on-insulator layer structure. The optical fiber adapter may include a mode converter, a trench, and a V-groove, the V-groove and the trench operating as passive alignment features for an optical fiber, in the transverse translational and rotational degrees of freedom, and in the longitudinal translational degree of freedom, respectively. The mode converter may include a buried tapered waveguide.Type: ApplicationFiled: May 1, 2020Publication date: August 13, 2020Inventors: John Drake, Damiana Lerose, Henri Nykänen, Gerald Cois Byrd
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Publication number: 20200243397Abstract: An optical mode converter and method of fabricating the same from wafer including a double silicon-on-insulator layer structure. The method comprising: providing a first mask over a portion of a device layer of the DSOI layer structure; etching an unmasked portion of the device layer down to at least an upper buried oxide layer, to provide a cavity; etching a first isolation trench and a second isolation trench into a mode converter layer, the mode converter layer being: on an opposite side of the upper buried oxide layer to the device layer and between the upper buried oxide layer and a lower buried oxide layer, the lower buried oxide layer being above a substrate; wherein the first isolation trench and the second isolation trench define a tapered waveguide; filling the first isolation trench and the second isolation trench with an insulating material, so as to optically isolate the tapered waveguide from the remaining mode converter layer; and regrowing the etched region of the device layer.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: John Drake, Damiana Lerose, Henri Nykänen
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Patent number: 10643903Abstract: An optical mode converter and method of fabricating the same from wafer including a double silicon-on-insulator layer structure. The method comprising: providing a first mask over a portion of a device layer of the DSOI layer structure; etching an unmasked portion of the device layer down to at least an upper buried oxide layer, to provide a cavity; etching a first isolation trench and a second isolation trench into a mode converter layer, the mode converter layer being: on an opposite side of the upper buried oxide layer to the device layer and between the upper buried oxide layer and a lower buried oxide layer, the lower buried oxide layer being above a substrate; wherein the first isolation trench and the second isolation trench define a tapered waveguide; filling the first isolation trench and the second isolation trench with an insulating material, so as to optically isolate the tapered waveguide from the remaining mode converter layer; and regrowing the etched region of the device layer.Type: GrantFiled: July 13, 2017Date of Patent: May 5, 2020Assignee: Rockley Photonics LimitedInventors: John Drake, Damiana Lerose, Henri Nykänen
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Patent number: 10641962Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and aType: GrantFiled: March 28, 2019Date of Patent: May 5, 2020Assignee: Rockley Photonics LimitedInventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
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Publication number: 20200124878Abstract: A Mach-Zehnder waveguide modulator. In some embodiments, the Mach-Zehnder waveguide modulator includes a first arm including a first optical waveguide, and a second arm including a second optical waveguide. The first optical waveguide includes a junction, and the Mach-Zehnder waveguide modulator further includes a plurality of electrodes for providing a bias across the junction to enable control of the phase of light travelling through the junction.Type: ApplicationFiled: August 23, 2019Publication date: April 23, 2020Inventors: Guomin Yu, Hooman Abediasl, Aaron L. Birkbeck, Jeffrey Driscoll, Haydn Frederick Jones, Damiana Lerose, Amit Singh Nagra, David Arlo Nelson, DongYoon Oh, Pradeep Srinivasan, Aaron John Zilkie