Patents by Inventor Damien Guillaume Pierre PAYET
Damien Guillaume Pierre PAYET has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11163691Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations, storage circuitry to store data for access by the processing circuitry, address translation circuitry to maintain address translation data for translating virtual memory addresses into corresponding physical memory addresses, and prefetch circuitry. The prefetch circuitry is arranged to prefetch first data into the storage circuitry in anticipation of the first data being required for performing the data processing operations. The prefetching comprises, based on a prediction scheme, predicting a first virtual memory address associated with the first data, accessing the address translation circuitry to determine a first physical memory address corresponding to the first virtual memory address, and retrieving the first data based on the first physical memory address corresponding to the first virtual memory address.Type: GrantFiled: June 25, 2019Date of Patent: November 2, 2021Assignee: ARM LIMITEDInventors: Stefano Ghiggini, Natalya Bondarenko, Damien Guillaume Pierre Payet, Lucas Garcia
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Patent number: 11138119Abstract: There is provided an apparatus that includes storage circuitry. The storage circuitry is made up from a plurality of sets, each of the sets having at least one storage location. Receiving circuitry receives an access request that includes an input address. Lookup circuitry obtains a plurality of candidate sets that correspond with an index part of the input address. The lookup circuitry determines a selected storage location from the candidate sets using an access policy. The access policy causes the lookup circuitry to iterate through the candidate sets to attempt to locate an appropriate storage location. The appropriate storage location is accessed in response to the appropriate storage location being found.Type: GrantFiled: January 15, 2019Date of Patent: October 5, 2021Assignee: Arm LimitedInventors: Damien Guillaume Pierre Payet, Natalya Bondarenko, Florent Begon, Lucas Garcia
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Patent number: 11055250Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.Type: GrantFiled: October 4, 2019Date of Patent: July 6, 2021Assignee: Arm LimitedInventors: Phanindra Kumar Mannava, Bruce James Mathewson, Klas Magnus Bruce, Damien Guillaume Pierre Payet, Jamshed Jalal, Alex James Waugh
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Patent number: 10990543Abstract: An apparatus and method are provided for arbitrating access to a set of resources that are to be accessed in response to requests received at an interface. Arbitration circuitry arbitrates amongst the requests received at the interface in order to select, in each arbitration cycle, at least one next request to be processed. Each request identifies an access operation to be performed in response to the request, the access operation being selected from a group of access operations. Further, each access operation in the group has an associated scheduling pattern identifying timing of access to the resources in the set when performing that access operation. In response to a given request being selected by the arbitration circuitry, access control circuitry controls access to the set of resources in accordance with the associated scheduling pattern for the access operation identified by that request.Type: GrantFiled: January 2, 2020Date of Patent: April 27, 2021Assignee: Arm LimitedInventors: Houdhaifa Bouzguarrou, Damien Guillaume Pierre Payet, Hugo Décharnes, Maxime Jean Carlo Philippe
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Publication number: 20210103543Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Inventors: Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Klas Magnus BRUCE, Damien Guillaume Pierre PAYET, Jamshed JALAL, Alex James WAUGH
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Patent number: 10956206Abstract: A technique is described for managing a cache structure in a system employing transactional memory. The apparatus comprises processing circuitry to perform data processing operations in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction, and a cache structure comprising a plurality of cache entries for storing data for access by the processing circuitry. Each cache entry has associated therewith an allocation tag, and allocation tag control circuitry is provided to control use of a plurality of allocation tags and to maintain an indication of a current state of each of those allocation tags.Type: GrantFiled: April 2, 2019Date of Patent: March 23, 2021Assignee: Arm LimitedInventors: Damien Guillaume Pierre Payet, Lucas Garcia, Natalya Bondarenko, Stefano Ghiggini
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Patent number: 10783031Abstract: An apparatus comprises processing circuitry, transactional memory support circuitry and a cache. The processing circuitry processes threads of data processing, and the transactional memory support circuitry supports execution of a transaction within a thread, including tracking a read set of addresses, comprising addresses accessed by read instructions within the transaction. A transaction comprises instructions for which the processing circuitry is configured to prevent commitment of the results of speculatively executed instruction until the transaction has completed. The cache has a plurality of entries, each associated with an address and specifying a replaceable-information value for that address that comprises information for which, outside of the transaction, processing would be functionally correct even if the information was incorrect.Type: GrantFiled: August 20, 2018Date of Patent: September 22, 2020Assignee: Arm LimitedInventors: Damien Guillaume Pierre Payet, Lucas Garcia, Natalya Bondarenko, Stefano Ghiggini
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Publication number: 20200065257Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations, storage circuitry to store data for access by the processing circuitry, address translation circuitry to maintain address translation data for translating virtual memory addresses into corresponding physical memory addresses, and prefetch circuitry. The prefetch circuitry is arranged to prefetch first data into the storage circuitry in anticipation of the first data being required for performing the data processing operations. The prefetching comprises, based on a prediction scheme, predicting a first virtual memory address associated with the first data, accessing the address translation circuitry to determine a first physical memory address corresponding to the first virtual memory address, and retrieving the first data based on the first physical memory address corresponding to the first virtual memory address.Type: ApplicationFiled: June 25, 2019Publication date: February 27, 2020Inventors: Stefano GHIGGINI, Natalya BONDARENKO, Damien Guillaume Pierre PAYET, Lucas GARCIA
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Publication number: 20200057692Abstract: An apparatus comprises processing circuitry, transactional memory support circuitry and a cache. The processing circuitry processes threads of data processing, and the transactional memory support circuitry supports execution of a transaction within a thread, including tracking a read set of addresses, comprising addresses accessed by read instructions within the transaction. A transaction comprises instructions for which the processing circuitry is configured to prevent commitment of the results of speculatively executed instruction until the transaction has completed. The cache has a plurality of entries, each associated with an address and specifying a replaceable-information value for that address that comprises information for which, outside of the transaction, processing would be functionally correct even if the information was incorrect.Type: ApplicationFiled: August 20, 2018Publication date: February 20, 2020Inventors: Damien Guillaume Pierre PAYET, Lucas GARCIA, Natalya BONDARENKO, Stefano GHIGGINI
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Publication number: 20190347124Abstract: A technique is described for managing a cache structure in a system employing transactional memory. The apparatus comprises processing circuitry to perform data processing operations in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction, and a cache structure comprising a plurality of cache entries for storing data for access by the processing circuitry. Each cache entry has associated therewith an allocation tag, and allocation tag control circuitry is provided to control use of a plurality of allocation tags and to maintain an indication of a current state of each of those allocation tags.Type: ApplicationFiled: April 2, 2019Publication date: November 14, 2019Inventors: Damien Guillaume Pierre PAYET, Lucas GARCIA, Natalya BONDARENKO, Stefano GHIGGINI
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Publication number: 20190220414Abstract: There is provided an apparatus that includes storage circuitry. The storage circuitry is made up from a plurality of sets, each of the sets having at least one storage location. Receiving circuitry receives an access request that includes an input address. Lookup circuitry obtains a plurality of candidate sets that correspond with an index part of the input address. The lookup circuitry determines a selected storage location from the candidate sets using an access policy. The access policy causes the lookup circuitry to iterate through the candidate sets to attempt to locate an appropriate storage location. The appropriate storage location is accessed in response to the appropriate storage location being found.Type: ApplicationFiled: January 15, 2019Publication date: July 18, 2019Inventors: Damien Guillaume Pierre PAYET, Natalya BONDARENKO, Florent BEGON, Lucas GARCIA