Abstract: Embodiments of the present disclosure may monitor and adjust a sampling rate of an ADC for converting the power signal to a digital signal, locking onto the phase and frequency of the power signal. This technique may make the sampling process coherent relative to the power signal. Properties of the power signal, such as phase, frequency, and magnitude, may be extracted relative to an idealized power signal.

Abstract: Techniques for determining a state of health of an energy storage device that utilize a capacitor gain amplifier to provide an AC gain and block the DC voltage. An input capacitor can couple between an input excitation signal generator circuit and the amplifier's inverting input terminal, and a feedback capacitor can couple between the amplifier's inverting input terminal and the amplifier's output. A switch can be used to reset the feedback capacitor periodically to prevent the amplifier's output from becoming saturated from a leakage current at the inverting input terminal of the amplifier.

Abstract: Techniques for determining a state of health of an energy storage device that utilize a capacitor gain amplifier to provide an AC gain and block the DC voltage. An input capacitor can couple between an input excitation signal generator circuit and the amplifier's inverting input terminal, and a feedback capacitor can couple between the amplifier's inverting input terminal and the amplifier's output. A switch can be used to reset the feedback capacitor periodically to prevent the amplifier's output from becoming saturated from a leakage current at the inverting input terminal of the amplifier.

Abstract: Embodiments of the present disclosure may monitor and adjust a sampling rate of an ADC for converting the power signal to a digital signal, locking onto the phase and frequency of the power signal. This technique may make the sampling process coherent relative to the power signal. Properties of the power signal, such as phase, frequency, and magnitude, may be extracted relative to an idealized power signal.

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

Abstract: A digital-to-analog conversion system includes a digital-to-analog converter and an output stage for converting an output signal of the digital-to-analog converter into a voltage range. The output stage includes a first amplifier including a first input for receiving the output signal of the digital-to-analog converter, a first resistance element coupled between a second input and an output of the first amplifier, a second resistance element coupled between the second input of the first amplifier and a ground reference, and a third resistance element switchably coupled from the second input of the first amplifier to an offset voltage.

Abstract: A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.

Abstract: A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.