Patents by Inventor Damien Ramonda

Damien Ramonda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic low power states characterization
    Patent number: 9733696
    Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: August 15, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nicole Chalhoub, Damien Ramonda, Francois Lacoste, Karine Bartolo, Vincent Bour
  • System constraints-aware scheduler for heterogeneous computing architecture
    Patent number: 9612879
    Abstract: Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 4, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Katrin Matthes, Damien Ramonda
  • DYNAMIC LOW POWER STATES CHARACTERIZATION
    Publication number: 20160154456
    Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Inventors: Nicole Chalhoub, Damien Ramonda, Francois Lacoste, Karine Bartolo, Vincent Bour
  • Dynamic low power states characterization
    Patent number: 9256274
    Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 9, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nicole Chalhoub, Damien Ramonda, François Lacoste, Karine Bartolo, Vincent Bour
  • DYNAMIC LOW POWER STATES CHARACTERIZATION
    Publication number: 20150039922
    Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.
    Type: Application
    Filed: December 20, 2013
    Publication date: February 5, 2015
    Applicant: Texas Instruments, Incorporated
    Inventors: Nicole CHALHOUB, Damien Ramonda, François LACOSTE, Karine BARTOLO, Vincent BOUR
  • SYSTEM CONSTRAINTS-AWARE SCHEDULER FOR HETEROGENEOUS COMPUTING ARCHITECTURE
    Publication number: 20150040136
    Abstract: Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters.
    Type: Application
    Filed: December 13, 2013
    Publication date: February 5, 2015
    Applicant: Texas Instruments, Incorporated
    Inventors: Katrin Matthes, Damien Ramonda