Patents by Inventor Damien Thomas
Damien Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935740Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.Type: GrantFiled: April 27, 2022Date of Patent: March 19, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mark Francis Arendt, Damien Thomas Gilmore
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Publication number: 20230420258Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.Type: ApplicationFiled: July 5, 2023Publication date: December 28, 2023Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
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Patent number: 11742208Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.Type: GrantFiled: March 25, 2020Date of Patent: August 29, 2023Assignee: Texas Instruments IncorporatedInventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
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Publication number: 20230245919Abstract: Described examples include a method having steps of forming an isolation pad oxide layer on a substrate and forming and patterning a silicon nitride layer on the isolation pad oxide layer. The method also has steps of oxidizing portions of the substrate not covered by the silicon nitride layer to form a LOCOS layer and oxidizing the silicon nitride layer in an oxidizing ambient containing a chlorine source to form a silicon dioxide layer.Type: ApplicationFiled: January 28, 2022Publication date: August 3, 2023Inventors: Mark Francis Arendt, Damien Thomas Gilmore
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Publication number: 20220254627Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.Type: ApplicationFiled: April 27, 2022Publication date: August 11, 2022Inventors: Mark Francis Arendt, Damien Thomas Gilmore
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Patent number: 11348782Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.Type: GrantFiled: March 31, 2020Date of Patent: May 31, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mark Francis Arendt, Damien Thomas Gilmore
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Publication number: 20210305050Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Applicant: Texas Instruments IncorporatedInventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
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Publication number: 20210305042Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.Type: ApplicationFiled: March 31, 2020Publication date: September 30, 2021Applicant: Texas Instruments IncorporatedInventors: Mark Francis Arendt, Damien Thomas Gilmore
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Patent number: 9939808Abstract: A method of process control for a batch process includes pre-measuring a monitor lot to obtain pre-metrology data regarding at least a first process parameter. There are no product units included with the monitor lot. The pre-metrology data is saved together with an identifier for the first monitor unit. A batch is staged for the batch process including at least a first product lot including a plurality of product units together with the first monitor unit. The batch is batch processed through the batch process. After the batch processing, the first monitor unit is measured to obtain post-metrology data for the first process parameter. At least one of the post-metrology data and a difference between the post-metrology data and pre-metrology data is saved to a data file with an identifier for the first product lot or the pre-metrology data and post-metrology data is directly written to the first product lot.Type: GrantFiled: December 15, 2014Date of Patent: April 10, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Damien Thomas Gilmore, Nicholas Andrew Kusek, Kenneth Ryan Thomas, Michael Glenn Williams, Robert Ray Spangler, Ingu Song
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Patent number: 9528997Abstract: The invention concerns an in vitro method for determining if an individual is infected by a bacterium of the Propionibacterium genus comprising: (i) detecting antibodies directed against at least one protein of sequence SEQ ID NO: 2, SEQ ID NO: 4, SEQ ID NO: 6 or SEQ ID NO: 8, in a biological sample of the individual, and (ii) deducing therefrom that the individual is infected by a bacterium of the Propionibacterium genus. The invention further concerns the kit for diagnosing of such an infection.Type: GrantFiled: November 14, 2012Date of Patent: December 27, 2016Assignee: DiaxonhitInventors: Julie Rogé, Hélène Nuyttens, Karine Mignon Godefroy, Damien Thomas, Virginie Pinchot
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Publication number: 20150253764Abstract: A method of process control for a batch process includes pre-measuring a monitor lot to obtain pre-metrology data regarding at least a first process parameter. There are no product units included with the monitor lot. The pre-metrology data is saved together with an identifier for the first monitor unit. A batch is staged for the batch process including at least a first product lot including a plurality of product units together with the first monitor unit. The batch is batch processed through the batch process. After the batch processing, the first monitor unit is measured to obtain post-metrology data for the first process parameter. At least one of the post-metrology data and a difference between the post-metrology data and pre-metrology data is saved to a data file with an identifier for the first product lot or the pre-metrology data and post-metrology data is directly written to the first product lot.Type: ApplicationFiled: December 15, 2014Publication date: September 10, 2015Inventors: DAMIEN THOMAS GILMORE, NICHOLAS ANDREW KUSEK, KENNETH RYAN THOMAS, MICHAEL GLENN WILLIAMS, ROBERT RAY SPANGLER, INGU SONG
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Patent number: 8101190Abstract: The present invention relates to a method for determining if an individual is infected by a staphylococcus bacterium, comprising: determining if antibodies directed against at least 2 proteins comprising a sequence selected from the group consisting of SEQ ID NO: 2, SEQ ID NO: 4, and SEQ ID NO: 6, are present in a biological sample of the individual, and deducing therefrom that the individual is infected by a staphylococcus bacterium.Type: GrantFiled: March 3, 2009Date of Patent: January 24, 2012Assignee: Ingen BiosciencesInventors: Camille Cyncynatus, Julie Roge, Damien Thomas, Helene Nuyttens
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Publication number: 20100227810Abstract: The present invention relates to a method for determining if an individual is infected by a staphylococcus bacterium, comprising: determining if antibodies directed against at least 2 proteins comprising a sequence selected from the group consisting of SEQ ID NO: 2, SEQ ID NO: 4, and SEQ ID NO: 6, are present in a biological sample of the individual, and deducing therefrom that the individual is infected by a staphylococcus bacterium.Type: ApplicationFiled: March 3, 2009Publication date: September 9, 2010Inventors: Camille Cyncynatus, Julie Roge, Damien Thomas, Helene Nuyttens