Patents by Inventor Damien Thomas

Damien Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935740
    Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: March 19, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mark Francis Arendt, Damien Thomas Gilmore
  • Publication number: 20230420258
    Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
    Type: Application
    Filed: July 5, 2023
    Publication date: December 28, 2023
    Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
  • Patent number: 11742208
    Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 29, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
  • Publication number: 20230245919
    Abstract: Described examples include a method having steps of forming an isolation pad oxide layer on a substrate and forming and patterning a silicon nitride layer on the isolation pad oxide layer. The method also has steps of oxidizing portions of the substrate not covered by the silicon nitride layer to form a LOCOS layer and oxidizing the silicon nitride layer in an oxidizing ambient containing a chlorine source to form a silicon dioxide layer.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 3, 2023
    Inventors: Mark Francis Arendt, Damien Thomas Gilmore
  • Publication number: 20220254627
    Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Inventors: Mark Francis Arendt, Damien Thomas Gilmore
  • Patent number: 11348782
    Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: May 31, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mark Francis Arendt, Damien Thomas Gilmore
  • Publication number: 20210305042
    Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Applicant: Texas Instruments Incorporated
    Inventors: Mark Francis Arendt, Damien Thomas Gilmore
  • Publication number: 20210305050
    Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
    Type: Application
    Filed: March 25, 2020
    Publication date: September 30, 2021
    Applicant: Texas Instruments Incorporated
    Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
  • Patent number: 9939808
    Abstract: A method of process control for a batch process includes pre-measuring a monitor lot to obtain pre-metrology data regarding at least a first process parameter. There are no product units included with the monitor lot. The pre-metrology data is saved together with an identifier for the first monitor unit. A batch is staged for the batch process including at least a first product lot including a plurality of product units together with the first monitor unit. The batch is batch processed through the batch process. After the batch processing, the first monitor unit is measured to obtain post-metrology data for the first process parameter. At least one of the post-metrology data and a difference between the post-metrology data and pre-metrology data is saved to a data file with an identifier for the first product lot or the pre-metrology data and post-metrology data is directly written to the first product lot.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: April 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Damien Thomas Gilmore, Nicholas Andrew Kusek, Kenneth Ryan Thomas, Michael Glenn Williams, Robert Ray Spangler, Ingu Song
  • Patent number: 9528997
    Abstract: The invention concerns an in vitro method for determining if an individual is infected by a bacterium of the Propionibacterium genus comprising: (i) detecting antibodies directed against at least one protein of sequence SEQ ID NO: 2, SEQ ID NO: 4, SEQ ID NO: 6 or SEQ ID NO: 8, in a biological sample of the individual, and (ii) deducing therefrom that the individual is infected by a bacterium of the Propionibacterium genus. The invention further concerns the kit for diagnosing of such an infection.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: December 27, 2016
    Assignee: Diaxonhit
    Inventors: Julie Rogé, Hélène Nuyttens, Karine Mignon Godefroy, Damien Thomas, Virginie Pinchot
  • Publication number: 20150253764
    Abstract: A method of process control for a batch process includes pre-measuring a monitor lot to obtain pre-metrology data regarding at least a first process parameter. There are no product units included with the monitor lot. The pre-metrology data is saved together with an identifier for the first monitor unit. A batch is staged for the batch process including at least a first product lot including a plurality of product units together with the first monitor unit. The batch is batch processed through the batch process. After the batch processing, the first monitor unit is measured to obtain post-metrology data for the first process parameter. At least one of the post-metrology data and a difference between the post-metrology data and pre-metrology data is saved to a data file with an identifier for the first product lot or the pre-metrology data and post-metrology data is directly written to the first product lot.
    Type: Application
    Filed: December 15, 2014
    Publication date: September 10, 2015
    Inventors: DAMIEN THOMAS GILMORE, NICHOLAS ANDREW KUSEK, KENNETH RYAN THOMAS, MICHAEL GLENN WILLIAMS, ROBERT RAY SPANGLER, INGU SONG
  • Patent number: 8101190
    Abstract: The present invention relates to a method for determining if an individual is infected by a staphylococcus bacterium, comprising: determining if antibodies directed against at least 2 proteins comprising a sequence selected from the group consisting of SEQ ID NO: 2, SEQ ID NO: 4, and SEQ ID NO: 6, are present in a biological sample of the individual, and deducing therefrom that the individual is infected by a staphylococcus bacterium.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: January 24, 2012
    Assignee: Ingen Biosciences
    Inventors: Camille Cyncynatus, Julie Roge, Damien Thomas, Helene Nuyttens
  • Publication number: 20100227810
    Abstract: The present invention relates to a method for determining if an individual is infected by a staphylococcus bacterium, comprising: determining if antibodies directed against at least 2 proteins comprising a sequence selected from the group consisting of SEQ ID NO: 2, SEQ ID NO: 4, and SEQ ID NO: 6, are present in a biological sample of the individual, and deducing therefrom that the individual is infected by a staphylococcus bacterium.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 9, 2010
    Inventors: Camille Cyncynatus, Julie Roge, Damien Thomas, Helene Nuyttens