Patents by Inventor Daming Jin
Daming Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150293865Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.Type: ApplicationFiled: June 2, 2015Publication date: October 15, 2015Inventors: Daming Jin, Vuong Cao Nguyen, Sam Shan-Jan Su, John Sui-Kei Tang, Peter Mark Fiacco
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Patent number: 9075797Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.Type: GrantFiled: December 2, 2013Date of Patent: July 7, 2015Assignee: EMULEX CORPORATIONInventors: Daming Jin, Vuong Cao Nguyen, Sam Shan-Jan Su, John Sui-Kei Tang, Peter Mark Fiacco
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Publication number: 20140095741Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.Type: ApplicationFiled: December 2, 2013Publication date: April 3, 2014Applicant: Emulex Design & Manufacturing CorporationInventors: Daming Jin, Vuong Cao Nguyen, Sam Shan-Jan Su, John Sui-Kei Tang, Peter Mark Fiacco
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Patent number: 8631169Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.Type: GrantFiled: June 6, 2008Date of Patent: January 14, 2014Assignee: Emulex Design & Manufacturing CorporationInventors: Daming Jin, Vuong Cao Nguyen, Sam Shan-Jan Su, John Sui-Kei Tang, Peter Mark Fiacco
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Patent number: 7853735Abstract: This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.Type: GrantFiled: December 13, 2007Date of Patent: December 14, 2010Assignee: Emulex Design & Manufacturing CorporationInventors: Daming Jin, Joe Chung-Ping Tien, Michael P. Yan, Vuong Cao Nguyen
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Patent number: 7765336Abstract: A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.Type: GrantFiled: June 11, 2007Date of Patent: July 27, 2010Assignee: Emulex Design & Manufacturing CorporationInventors: Jim Donald Butler, Joe Chung-Ping Tien, Daming Jin
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Publication number: 20100064072Abstract: A network arbitration scheme is disclosed that manages device access fairness by selectively and dynamically increasing a requestor queue's likelihood of being serviced. A requestor queue increases its service priority by duplicating a request entry onto a set of priority rings maintained by arbitration hardware in a host bus adapter. Duplication occurs when (1) a requestor's queue fill count (the number of descriptors stored in the queue) exceeds a watermark level or (2) a requestor's queue timer times out. In the case of time-out, the requester in the lower priority ring will duplicate itself in the higher priority ring. Because the arbitration hardware services requesters using a round robin selection scheme, the likelihood of a requestor queue being serviced increases as the number of its duplicate request entries on a priority ring increases. Upon being serviced, the requester is able to perform the requested action.Type: ApplicationFiled: September 9, 2008Publication date: March 11, 2010Applicant: Emulex Design & Manufacturing CorporationInventors: John Sui-kei Tang, Sam Shan-Jan Su, Michael Yu Liu, Daming Jin
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Publication number: 20100023748Abstract: The present invention is related to the checking of encryption. Embodiments of the present invention are based on the discovery that sufficiently high reliability may be established without checking every encryption block. Instead, embodiments of the present invention provide that data being encrypted may be sampled at certain rate (which may be constant or varying) and only the sampled data may be checked. In general, embodiments of the present inventions are applicable to a fast encryption circuit that may encrypt an entire stream of incoming data into a stream of encrypted data and one or more slower (or slow) encryption circuit and/or one or more slow decryption circuit that operate(s) only on selected samples of the incoming or encrypted data in order to check the encryption of the fast circuit. Thus, encryption can be verified without incurring the costs of exhaustively checking all encrypted data.Type: ApplicationFiled: December 28, 2007Publication date: January 28, 2010Applicant: Emulex Design & Manufacturing CorporationInventors: John Sui-Kei TANG, Daming JIN, Jim Donald BUTLER, Jeff Junwei ZHENG
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Publication number: 20090307386Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.Type: ApplicationFiled: June 6, 2008Publication date: December 10, 2009Inventors: Daming JIN, Vuong Cao Nguyen, Sam Shan-Jan Su, John Sui-kei Tang, Peter Mark Fiacco
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Publication number: 20090157918Abstract: This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Applicant: Emulex Design & Manufacturing CorporationInventors: Daming JIN, Joe Chung-Ping Tien, Michael P. Yan, Vuong Cao Nguyen
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Publication number: 20080307122Abstract: A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.Type: ApplicationFiled: June 11, 2007Publication date: December 11, 2008Applicant: Emulex design & Manufacturing CorporationInventors: Jim Donald Butler, Joe Chung-Ping Tien, Daming Jin
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Patent number: 7149823Abstract: A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.Type: GrantFiled: August 29, 2003Date of Patent: December 12, 2006Assignee: Emulex CorporationInventors: Eddie Miller, David James Duckman, Jim Donald Butler, Daming Jin, John Sui-Kei Tang
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Publication number: 20050050245Abstract: A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.Type: ApplicationFiled: August 29, 2003Publication date: March 3, 2005Inventors: Eddie Miller, David Duckman, Jim Butler, Daming Jin, John Tang
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Patent number: 6687262Abstract: The inventive control logic provides the selection signals for a bi-endian rotator MUX. The logic determines the starting point for the data transfer by determining which input register byte is going to Byte 0 of the output register. The control logic passes the starting point to single decoder. The decoded value is then sent to a plurality of MUXs, one for each of the output register bytes. Each of the MUXs is prewired to receive a portion of bits of the decoded value, and the portion is arranged in a particular order. The MUXs then send their respective outputs to the rotator MUX as selection control signals.Type: GrantFiled: February 21, 2000Date of Patent: February 3, 2004Assignees: Hewlett-Packard Development Company, L.P., Intel CorporationInventors: Daming Jin, Dean A. Mulla, Douglas J Cutter, Thomas Grutkowski
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Patent number: 6658505Abstract: A computer hardware system is disclosed for determining during a single clock cycle whether a data buffer having a plurality of entries can accept additional data. The system has multiple stages, having one or more adders/encoders that process the data buffer entries' valid bits in parallel. Groups of entries are associated with first-stage adders/encoders. Valid bits and their complements for entries in each group are received into multiple first-stage adders that compute and output encoded values indicating the number of available entries within each group, or first-stage totals. The adders also encode the first-stage totals such that a saturated count corresponds to a pre-charged state of the first-stage adder. The first-stage totals are then sent to additional stages having adders/encoders that are substantially the same as the first-stage adders/encoders. The additional-stage adders combine the encoded totals from prior stages and determine whether the buffer has available entries.Type: GrantFiled: June 5, 2001Date of Patent: December 2, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Daming Jin, Timothy C. Fischer
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Publication number: 20020184414Abstract: A computer hardware system is disclosed for determining during a single clock cycle whether a data buffer having a plurality of entries can accept additional data. The system has multiple stages, having one or more adders/encoders that process the data buffer entries' valid bits in parallel. Groups of entries are associated with first-stage adders/encoders. Valid bits and their complements for entries in each group are received into multiple first-stage adders that compute and output encoded values indicating the 8 number of available entries within each group, or first-stage totals. The adders also encode the first-stage totals such that a saturated count corresponds to a pre-charged state of the first-stage adder. The first-stage totals are then sent to additional stages having adders/encoders that are substantially the same as the first-stage adders/encoders. The additional-stage adders combine the encoded totals from prior stages and determine whether the buffer has available entries.Type: ApplicationFiled: June 5, 2001Publication date: December 5, 2002Inventors: Daming Jin, Timothy C. Fischer
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Patent number: 6470374Abstract: The inventive adder can perform carry look-ahead calculations for a bi-endian adder in a cache memory system. The adder can add one of +/−1, 4, 8, or 16 to a loaded value from memory, and the operation can be a 4 or 8 byte add. The inventive adder comprises a plurality of byte adder cells and carry look-ahead (CLA) logic. The adder cells determine which of themselves is the least significant bit (LSB) byte adder cell. The LSB cell then adds one of the increment values to its loaded value. The other cells add 0x00 or 0xFF, depending upon the sign of the increment value, to a loaded value from memory. Each adder performs two adds, one for a carry-in of 0, and the other for a carry in of 1. Both results are sent to a MUX. The CLA logic determines each of the carries, and provides a selection control signal to each MUX. of the different cells.Type: GrantFiled: February 21, 2000Date of Patent: October 22, 2002Assignees: Hewlett-Packard Company, Intel CorporationInventors: Daming Jin, Dean A. Mulla, Tom Grutkowski