Patents by Inventor Damir Fazil

Damir Fazil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220301860
    Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 22, 2022
    Inventors: John D. Hopkins, Damir Fazil
  • Patent number: 11430809
    Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: S. M. Istiaque Hossain, Prakash Rau Mokhna Rau, Arun Kumar Dhayalan, Damir Fazil, Joel D. Peterson, Anilkumar Chandolu, Albert Fayrushin, George Matamis, Christopher Larsen, Rokibul Islam
  • Patent number: 11393672
    Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Damir Fazil
  • Patent number: 11329062
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Erik Byers, Merri L. Carlson, Indra V. Chary, Damir Fazil, John D. Hopkins, Nancy M. Lomeli, Eldon Nelson, Joel D. Peterson, Dimitrios Pavlopoulos, Paolo Tessariol, Lifang Xu
  • Publication number: 20220045086
    Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Applicant: Micron Technology, Inc.
    Inventors: S.M. Istiaque Hossain, Prakash Rau Mokhna Rau, Arun Kumar Dhayalan, Damir Fazil, Joel D. Peterson, Anilkumar Chandolu, Albert Fayrushin, George Matamis, Christopher Larsen, Rokibul Islam
  • Publication number: 20210358951
    Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Nirup Bandaru, Damir Fazil, Nancy M. Lomeli, Jivaan Kishore Jhothiraman, Purnima Narayanan
  • Patent number: 11107831
    Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Nirup Bandaru, Damir Fazil, Nancy M. Lomeli, Jivaan Kishore Jhothiraman, Purnima Narayanan
  • Publication number: 20210249261
    Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 12, 2021
    Inventors: John D. Hopkins, Damir Fazil
  • Patent number: 11056497
    Abstract: A method used in forming a memory array comprises forming a conductive tier atop a substrate, with the conductive tier comprising openings therein. An insulator tier is formed atop the conductive tier and the insulator tier comprises insulator material that extends downwardly into the openings in the conductive tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the insulator tier. Strings comprising channel material that extend through the insulative tiers and the wordline tiers are formed. The channel material of the strings is directly electrically coupled to conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Damir Fazil, Nancy M. Lomeli
  • Publication number: 20210167081
    Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Nirup Bandaru, Damir Fazil, Nancy M. Lomeli, Jivaan Kishore Jhothiraman, Purnima Narayanan
  • Publication number: 20210013228
    Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: John D. Hopkins, Nancy M. Lomeli, Justin B. Dorhout, Damir Fazil
  • Publication number: 20200357809
    Abstract: A method used in forming a memory array comprises forming a conductive tier atop a substrate, with the conductive tier comprising openings therein. An insulator tier is formed atop the conductive tier and the insulator tier comprises insulator material that extends downwardly into the openings in the conductive tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the insulator tier. Strings comprising channel material that extend through the insulative tiers and the wordline tiers are formed. The channel material of the strings is directly electrically coupled to conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Damir Fazil, Nancy M. Lomeli
  • Patent number: 10825828
    Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli, Justin B. Dorhout, Damir Fazil
  • Publication number: 20200127004
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Erik Byers, Merri L. Carlson, Indra V. Chary, Damir Fazil, John D. Hopkins, Nancy M. Lomeli, Eldon Nelson, Joel D. Peterson, Dimitrios Pavlopoulos, Paolo Tessariol, Lifang Xu
  • Publication number: 20200119038
    Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: John D. Hopkins, Nancy M. Lomeli, Justin B. Dorhout, Damir Fazil
  • Patent number: 10134758
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil
  • Publication number: 20180130819
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Application
    Filed: August 22, 2017
    Publication date: May 10, 2018
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil
  • Patent number: 9741734
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil
  • Publication number: 20170170190
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil