Abstract: A method is provided for prioritizing the entries in a database, where each entry is composed of multiple dimensions. Prioritization is required when there are multiple matches in the database. The number of matches can be the same as the number of entries in the database. To prioritize such a huge number of entries in a minimum number of clock cycles, a distributed prioritizer is implemented by partitioning stored binary data into half nibbles comprising of two bits of data each. Each half nibble is encoded into an expanded format allotting priority value to the stored encoded half nibbles. The stored encoded half nibbles are compared across a word array to determine an exact match.

Abstract: A range check array structure for searching and comparing external data from an external search data key is disclosed. The structure has data storage means with at least one of an upper limit field, and a lower limit field, and one or more bit lines running therethrough for transmitting an input data word for comparison with the stored data word range. The input data word being compared with a respective stored data word to detect a match that is indicated along a match line by the check array structure. The check array structure further includes a range match detection means connected to the match line to determine the match or mismatch of the applied data stream with the stored data in each range check cell.

Abstract: A range check array structure for searching and comparing external data from an external search data key is disclosed. The structure has data storage means with at least one of an upper limit field, and a lower limit field, and one or more bit lines running therethrough for transmitting an input data word for comparison with the stored data word range. The input data word being compared with a respective stored data word to detect a match that is indicated along a match line by the check array structure. The check array structure further includes a range match detection means connected to the match line to determine the match or mismatch of the applied data stream with the stored data in each range check cell.

Abstract: A method is provided for prioritizing the entries in a database, where each entry is composed of multiple dimensions. Prioritization is required when there are multiple matches in the database. The number of matches can be the same as the number of entries in the database. To prioritize such a huge number of entries in a minimum number of clock cycles, a distributed prioritizer is implemented by partitioning stored binary data into half nibbles comprising of two bits of data each. Each half nibble is encoded into an expanded format allotting priority value to the stored encoded half nibbles. The stored encoded half nibbles are compared across a word array to determine an exact match.

Abstract: An intelligent content addressable memory (CAM) cell for CIDR co-processors is disclosed. The CAM cell is operative to search and compare external data from an external search data key with stored data. The CAM cell comprises means for containing the stored data and means for enabling a mask prefix read path for a work matching the external search data key. Furthermore, the CAM cell includes means for merging a mask prefix pattern of all matching entries in order to generate a device longest prefix match. A comparison is made between the device longest prefix match and word mask prefix data in order to find the desired data.

Abstract: A flash memory architecture relies on a single, time-shared address bus to enable a read operation to be performed simultaneously with an algorithm operation when the read operation is targeted for a memory cell block that is not currently tagged for an algorithm operation. After a read address has been latched into the array block selected for the read operation, the address bus is "free" for the remainder of the read operation cycle. During this free time, the address bus can be used for algorithm operations to load the counter address into an active tagged block in the array. Separate global data I/O lines are provided to facilitate simultaneous read and algorithm operations.