Abstract: An embodiment of a transistor die includes a semiconductor substrate a drain region, a channel region, a drain terminal, and a conductive gate tap. The conductive gate tap includes a distal end that is coupled to a gate structure over the channel region. A first segment of the drain region is adjacent to the distal end of the gate tap. The drain terminal includes a drain runner formed from one or more portions of the patterned conductive layers. A plurality of drain pillars electrically connects the drain runner to second and third segments of the drain region, and a plurality of second drain pillars electrically connect the drain runner and the third drain region segment. The build-up structure over the second drain region segment between the first and second drain pillars is devoid of electrical connections between the drain runner and the drain region.

Abstract: A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of multiple layers of dielectric material and electrically conductive material on an upper surface of the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure formed from the electrically conductive material. The pillar electrically contacts the first terminal, extends through the dielectric material, and connects to a first runner. The tap interconnect electrically contacts the second terminal, extends through the dielectric material, and connects to a second runner. The shield structure extends from a shield runner through the dielectric material toward the semiconductor substrate. The shield structure is positioned between the pillar and the tap interconnect to limit feedback capacitance between the tap interconnect and the pillar.