Patents by Inventor Damon Philippe

Damon Philippe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9215125
    Abstract: A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=<n×s/m.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: December 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Jean L. Calvignac, Chih-Jen Chang, Damon Philippe, Natarajan Vaidhyanathan, Colin B. Verrilli, Fabrice Jean Verplanken
  • Publication number: 20130308653
    Abstract: A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=<n×s/m.
    Type: Application
    Filed: December 19, 2011
    Publication date: November 21, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Claude Basso, Jean L. Calvignac, Chih-Jen Chang, Damon Philippe, Natarajan Vaidhyanathan, Colin B. Verrilli, Fabrice Jean Verplanken
  • Publication number: 20130266021
    Abstract: The invention provides a method for adding specific hardware on both receive and transmit sides that will hide to the software most of the effort related to buffer and pointers management. At initialization, a set of pointers and buffers is provided by software, in quantity large enough to support expected traffic. A Send Queue Replenisher (SQR) and Receive Queue Replenisher (RQR) hide RQ and SQ management to software. RQR and SQR fully monitor pointers queues and perform recirculation of pointers from transmit side to receive side.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 10, 2013
    Inventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Damon Philippe, Michel L. Poret, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli