Patents by Inventor Damon Tohidi
Damon Tohidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11805026Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.Type: GrantFiled: August 14, 2020Date of Patent: October 31, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Stanley Ames Lackey, Jr., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
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Patent number: 11283589Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.Type: GrantFiled: December 21, 2020Date of Patent: March 22, 2022Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
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Publication number: 20210111861Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
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Publication number: 20210028995Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.Type: ApplicationFiled: August 14, 2020Publication date: January 28, 2021Inventors: Stanley Ames Lackey, JR., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
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Patent number: 10873445Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.Type: GrantFiled: December 10, 2019Date of Patent: December 22, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
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Publication number: 20200344039Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.Type: ApplicationFiled: December 10, 2019Publication date: October 29, 2020Inventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
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Patent number: 10755010Abstract: An indeterminate state representative of a metastable state is inserted into an output signal of a circuit representation responsive to the circuit representation receiving a metastable triggering event during a register transfer language (RTL) simulation. The simulation view of the RTL has been modified to ensure that the indeterminate state is propagated through the circuit representations regardless of the input on which the indeterminate state appears. The indeterminate state is maintained for a programmable amount of time and responsive to expiration of the amount of time, the output signal is set to a random binary value.Type: GrantFiled: September 24, 2018Date of Patent: August 25, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Shalini Sodagam, Anandh Ganesan, Nandeesh Thimmappa, Damon Tohidi
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Patent number: 10749756Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.Type: GrantFiled: June 24, 2016Date of Patent: August 18, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Stanley Ames Lackey, Jr., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
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Publication number: 20200097626Abstract: An indeterminate state representative of a metastable state is inserted into an output signal of a circuit representation responsive to the circuit representation receiving a metastable triggering event during a register transfer language (RTL) simulation. The simulation view of the RTL has been modified to ensure that the indeterminate state is propagated through the circuit representations regardless of the input on which the indeterminate state appears. The indeterminate state is maintained for a programmable amount of time and responsive to expiration of the amount of time, the output signal is set to a random binary value.Type: ApplicationFiled: September 24, 2018Publication date: March 26, 2020Inventors: Shalini Sodagam, Anandh Ganesan, Nandeesh Thimmappa, Damon Tohidi
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Patent number: 10581587Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.Type: GrantFiled: April 29, 2019Date of Patent: March 3, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
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Patent number: 10103837Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of āNā clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.Type: GrantFiled: June 23, 2016Date of Patent: October 16, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Stanley Ames Lackey, Jr., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
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Publication number: 20170373788Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of āNā clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.Type: ApplicationFiled: June 23, 2016Publication date: December 28, 2017Inventors: Stanley Ames Lackey, JR., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
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Publication number: 20170373944Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.Type: ApplicationFiled: June 24, 2016Publication date: December 28, 2017Inventors: Stanley Ames Lackey, JR., Damon Tohidi, Gerald R. Talbot, Edoardo Prete