Patents by Inventor Damon W. Finney

Damon W. Finney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6101194
    Abstract: Conflicts are resolved between competing nodes in a multi-node communications network. After a first node in the network requests an initiation of communications with a target node, the requesting node may simply initiate the requested communications with the target node if the target node is not busy. If the first node determines that the target node is busy, it proceeds to resolve the conflict. Namely, the first node repeats the process of waiting for a first delay then requesting initiation of communications with the target node. After each unsuccessful attempt, the first delay is successively increased. As an example, the delay may be increased exponentially, with a controlled randomness added. After a or more queued messages to other nodes. Following this, the first node performs another sequence to initiate communications with the target node, successively increasing the delay between unsuccessful attempts, as before.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: August 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: Narasimha Lakshmi Annapareddy, James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Jai M. Menon, David Ronald Nowlen
  • Patent number: 5940612
    Abstract: A procedure controls execution of priority ordered tasks in a multi-nodel data processing system. The data processing system includes a node with a software-controlled processor and a hardware-configured queue-controller. The queue-controller includes a plurality of priority-ordered queues, each queue listing tasks having an assigned priority equal to a priority order assigned to the queue.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: August 17, 1999
    Assignee: International Business Machines Corporation
    Inventors: James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Noah R. Mendelsohn, Jaishankar Moothedath Menon, David R. Nowlen
  • Patent number: 5860088
    Abstract: A method enables a host processor, which employs variable length (VL) records, to transparently communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: January 12, 1999
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Donald J. Lang, Jaishankar Moothedath Menon
  • Patent number: 5857213
    Abstract: A method enables a host processor, which employs variable length (VL) records, to communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: January 5, 1999
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Donald J. Lang, Jaishankar Moothedath Menon
  • Patent number: 5845072
    Abstract: A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: December 1, 1998
    Assignee: International Business Machines Corporation
    Inventors: Damon W. Finney, Wen-Jei Ho, Mark C. Johnson, Donald J. Lang
  • Patent number: 5784698
    Abstract: An apparatus for dynamically allocating memory includes a processor, a free buffer pool memory and a control memory which stores control block data structures. The control block data structures enable a segmentation of the free buffer pool memory into a series of free buffer pools, each free buffer pool comprising plural identical size buffers, each succeeding free buffer pool including a larger buffer size than a preceding free buffer pool. A selection size parameter for a given free buffer pool is a value that is larger than the buffer size comprising the given free buffer pool, but less than a next larger buffer size in the next of the series of free buffer pools.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: July 21, 1998
    Assignee: International Business Machines Corporation
    Inventors: James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Michael Anthony Ko, Noah R. Mendelsohn, Jaishankar Moothedath Menon, David R. Nowlen
  • Patent number: 5717862
    Abstract: A multi-nodal data processing system includes a plurality of processing nodes, each node connected to plural other nodes by bidirectional data links. Each node comprises receivers for receiving messages on bidirectional data links and transmitters for transmitting messages on bidirectional data links. Each node records child nodes to which a message was transmitted and is further adapted to transmit a lock-up message received from a child node to a parent node, the lock-up message indicating a successful establishment of a message signal path to a destination node. Each node further is adapted to transmit a link cancel signal to another node to close the link in the event of an unsuccessful message transfer attempt over the link. Each node inhibits transmission of a lock-up signal to a parent node until link cancel signals have been received from all child nodes (other than a node from which a lock-up signal was received).
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: February 10, 1998
    Assignee: International Business Machines Corporation
    Inventors: Narasimhareddy L. Annapareddy, James Thomas Brady, Damon W. Finney, Richard F. Freitas, Michael Anthony Ko, Michael James Rayfield
  • Patent number: 5712856
    Abstract: A test link protocol which continuously monitors each link in a network to ensure that the link is correctly transmitting data. Each switch, or torus has at least one of two functional components: Send Test and Receive Test. The Send Test component monitors control codes at a torus link output. The Receive Test component monitors control codes at a torus link input. After a predetermined interval, the Send Test component makes a request to send a test.sub.-- link control code. The torus sends the test.sub.-- link code to the neighboring torus, where it is removed from the data stream and sent to that torus' Receive Test. The Receive Test then generates a response message and makes a request to send that message back to the originating torus. After receiving the message, the Send Test analyzes the message to determine whether the network link is working correctly. An error is also declared if the Send Test does not receive a reply within a predetermined interval.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: January 27, 1998
    Assignee: International Business Machines Corporation
    Inventors: Damon W. Finney, Michael James Rayfield
  • Patent number: 5706443
    Abstract: A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting.
    Type: Grant
    Filed: May 11, 1994
    Date of Patent: January 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: James T. Brady, Damon W. Finney, Michael H. Hartung, Donald J. Lang, Jaishankar M. Menon, David R. Nowlen, Calvin K. Tang
  • Patent number: 5687393
    Abstract: A data processing system includes one or more processors connected to a common bus, one or more I/O controllers connected to the common bus and to one or more storage subsystems and one or more storage subsystems for storing data for use in the data processing system. One or more master controllers are included in each I/O controller for communicating with a memory controller referred to as a slave which controls data flow to and from a memory subsystem. The data bus between the I/O masters and the memory controller is a multi-drop operating synchronously on a two-by-two byte parallel interface.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Marcel Brown, Damon W. Finney, George Bohoslaw Marenin, Adalberto Guillermo Yanes
  • Patent number: 5675736
    Abstract: A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages and a control memory for storing the control messages. Each node further includes data message line for handling of data messages and a data memory for storing the data messages. A processor in the node causes the data message line to queue and dispatch data messages from the data memory and the control message line to queue and dispatch control messages from the control memory. Each node includes N bidirectional communication links enabling the node to have at least twice as much input/output bandwidth as the control message line and data message line, combined. An input/output switch includes a routing processor and is coupled between the N bidirectional communication links, the data message line and control message line.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: October 7, 1997
    Assignee: International Business Machines Corporation
    Inventors: James Thomas Brady, Damon W. Finney, Michael Howard Hartung, Paul Wayne Hunter, Michael Anthony Ko, Donald J. Lang, Noah R. Mendelsohn, Jaishankar Moothedath Menon, David Ronald Nowlen
  • Patent number: 5630059
    Abstract: A multi-nodal computing system is connected by a communication network. A first node of the multi-nodal system includes apparatus for transmitting an information transfer request to a second node, the request including identification data that the second node can use to access the selected information. The second node includes memory for storing the requested information and a message output control structure. A processor is responsive to received identification data from the first node to access selected information that is defined by the data. The processor is further responsive to the information transfer request to insert the identification data received from the first node directly into a message output control structure. The processor then initiates an output operation by employing the identification data in the message output control data structure to access the identified information and to communicate the information to the first node.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: May 13, 1997
    Assignee: International Business Machines Corporation
    Inventors: James T. Brady, Damon W. Finney, David R. Nowlen
  • Patent number: 5613067
    Abstract: A multi-node data processing system implements a method that assures that plural messages are enabled "fair" access to a data stream. Each node includes apparatus for controlling message transmissions and/or receptions from another node over a communication network. The method comprises the steps of: transmitting a routing message from a first destination node to a source node, the routing message signalling a readiness of the destination node to receive a data message; transmitting a first data message to the first destination node from the source node in response to the ready message; transmitting a conditional disconnect message from the first destination node to the source node upon receipt of a predetermined amount (i.e. a "slice") of the first data message.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: March 18, 1997
    Assignee: International Business Machines Corporation
    Inventors: James T. Brady, Damon W. Finney, Donald J. Lang, George B. Marenin, David Nowlen
  • Patent number: 5606703
    Abstract: A data processing system includes a software interrupt handler which controls performance of interrupt actions. The system further includes plural subsystems, each subsystem manifesting an interrupt request upon occurrence of an associated event. Hardware is provided which responds to an interrupt request by issuing an order to construct an interrupt status block (ISB) control data structure with a determined priority ranking. A controller is responsive to the issued order and constructs the ISB data structure. The ISB at least includes a pointer value indicating a next ISB having a same priority ranking, interrupt data identifying an interrupt procedure to be used by the software interrupt handler and information indicating a source of the interrupt request. The controller arranges the ISB in a queue of ISB's having a same determined priority and signals the software interrupt handler to commence performance of an interrupt action only if the order issued by the hardware requires an immediate interrupt.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: February 25, 1997
    Assignee: International Business Machines Corporation
    Inventors: James T. Brady, Damon W. Finney
  • Patent number: 5602839
    Abstract: In a multinode communication or multiprocessor network, messages are communicated from one node to another using an adaptive and dynamic routing scheme. The routing scheme includes two-level multi-path routing tables at each node to ensure efficient delivery of the messages. An entry in the level-1 table identifies a group of nodes and entry in the level-2 table identifies the address for each node within that group. The routing scheme also includes a deflection counter in each message header to avoid endless rerouting of messages and an exponential backoff and retry policy to avoid deadlocks.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: February 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: Narasimhareddy Annapareddy, James T. Brady, Damon W. Finney
  • Patent number: 5603044
    Abstract: An interconnection network comprises a pair of backplanes for receiving X pluggable node cards. The pair of backplanes include X backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group includes X/2 connectors. A first backplane includes first permanent wiring which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane includes second permanent wiring which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets' of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: February 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: Narasimhareddy L. Annapareddy, Damon W. Finney, Michael O. Jenkins, Larry B. Kessler, Donald J. Lang, Song C. Liang, David N. Mora, David A. Plomgren, Peter P. Urbisci, Andrew D. Walls
  • Patent number: 5577211
    Abstract: A computing system includes plural nodes that are connected by a communications network. Each node comprises a communications interface that enables an exchange of messages with other nodes. A ready queue is maintained in a node and includes plural message entries, each message entry indicating an output message control data structure. The node further includes memory for storing plural output message control data structures, each including one or more chained further monrtol data structures that define data comprising a message or a portion of a message that is to be dispatched. Control data structures that are chained from an output messsage control data structure exhibit a sequence dependincy. A processor is controlled by the ready queue and enables dispatch of portions of the message designated by an output message control data structure and associated further control structures.
    Type: Grant
    Filed: May 11, 1994
    Date of Patent: November 19, 1996
    Assignee: IBM Corporation
    Inventors: Narasimhareddy L. Annapareddy, James T. Brady, Damon W. Finney, Richard F. Freitas, Michael H. Hartung, Michael A. Ko, Noah R. Mendelsohn, Jaishankar M. Menon, David R. Nowlen, Shin-Yuan Tzou
  • Patent number: 5570356
    Abstract: A data communication system includes a phase splitting circuit to split a high speed parallel data word into a number of individual parallel data bytes, a byte multiplexor for each of the phases of a phase splitting circuit, encoding and serialization circuits for converting each byte such as an 8-bit byte to an encoded form suitable for serial transmission such as by employing the Widmer et al. 8-bit/10-bit code, transmitting each encoded byte across one of a number of serial transmission links to a receiving device where the data is deserialized and decoded to recover the original byte which is then synchronized by a byte synchronization circuit. The byte synchronization circuits are then coupled to a word synchronization circuit where the original high bandwidth data word is recovered and transmitted on an internal high speed parallel bus within the receiving device.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 29, 1996
    Assignee: International Business Machines Corporation
    Inventors: Damon W. Finney, Michael O. Jenkins, Michael J. Rayfield
  • Patent number: 5487092
    Abstract: A high-performance clock synchronizer for transferring digital data across the asynchronous boundary between two independent clock domains operating at hardware-limited clock speeds. The external clock signal latches each incoming data word in a boundary register. An external clock divider produces several prolonged clock signals synchronized to the external clock signal for use in distributing the incoming data words into a bank of several external buffer registers, where each word stabilizes for more than one full internal clock interval before transfer across the asynchronous boundary to a bank of corresponding internal buffer registers synchronized to the internal clock signal. A special logic inserts and deletes pad words to equalize data flow rates. Another special logic reassembles the data words in proper sequence after transfer to the internal buffer register bank. Flag latches are used to avoid asynchronous sampling of more than one bit in each data word.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: January 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: Damon W. Finney, Michael J. Rayfield