Abstract: An electronic circuit includes an adaptive delay circuit and a test circuit. The adaptive delay circuit is configured to receive an input clock signal, to further receive a delay setting that specifies first and second delays, and to generate first and second delayed versions of the input clock signal that are delayed relative to the input clock signal by the first and second delays, respectively. The test circuit is configured to test the adaptive delay circuit by (i) programming the adaptive delay circuit with multiple different delay settings that each specifies a respective first delay and a respective second delay, (ii) for each of the multiple delay settings, measuring an actual time offset between the first and second delayed versions of the input clock signal, and (iii) generating a test result based on actual time offsets measured for the multiple different delay settings.

Abstract: A stream parser for receiving, parsing, and/or pre-processing network data traffic directly from an incoming unreconstructed data stream. To extract meaningful data from the unreconstructed data stream, the stream parser employs a context switch module for re-forming parts of packet headers as the data stream is streaming through the stream parser. The stream parser includes a logic unit operated by microcode stored in a program module, as well as a channel configuration memory controlled by software in a master processor. Because of this combination of hardware processing and software control, the stream parser is both quick and flexible.