Abstract: A communications device is provided. The communications device includes a first antenna port coupled to a signal line, transmitter circuitry coupled to the signal line and configured to broadcast a radio frequency (RF) output signal across the first antenna port, tuning circuitry coupled to the signal line, and a controller configured to adjust a tuning of the tuning circuitry. The first antenna port, the transmitter circuitry, the tuning circuitry, and the controller are at least partially integrated on the same integrated circuit.

Abstract: A communications device is provided. The communications device includes a first antenna port coupled to a signal line, transmitter circuitry coupled to the signal line and configured to broadcast a radio frequency (RF) output signal across the first antenna port, tuning circuitry coupled to the signal line, and a controller configured to adjust a tuning of the tuning circuitry. The first antenna port, the transmitter circuitry, the tuning circuitry, and the controller are at least partially integrated on the same integrated circuit.

Abstract: In one embodiment, the present invention includes an amplifier having an input to receive a radio frequency (RF) signal from an output node of a source. An input stage coupled to the amplifier input may include one or more components to aid in processing of incoming signals. One such component coupled between the source and the input of the amplifier is a coupling capacitor used to maintain a bias voltage of the amplifier at a different potential than a DC voltage of the output node. In certain applications, the amplifier and the coupling capacitor may be integrated on a single substrate.

Abstract: In one embodiment, the present invention includes an amplifier having an input to receive a radio frequency (RF) signal from an output node of a source. An input stage coupled to the amplifier input may include one or more components to aid in processing of incoming signals. One such component coupled between the source and the input of the amplifier is a coupling capacitor used to maintain a bias voltage of the amplifier at a different potential than a DC voltage of the output node. In certain applications, the amplifier and the coupling capacitor may be integrated on a single substrate.

Abstract: Integrated low-IF (low intermediate frequency) data receivers and associated methods are disclosed that provide advantageous and cost-efficient solutions.

Abstract: Receiver architectures and related methods are disclosed for high definition (HD) and digital radio FM broadcast receivers. The radio receiver architectures are configured to utilize multiple analog-to-digital converters (ADCs) to handle the digital radio spectrum and can be configured to modify a target IF frequencies depending upon the mode of operation of the receiver. For example, the receiver can include an analog FM reception mode and a digital FM reception mode for which different down-conversions are used for the same analog-plus-digital audio broadcast channel. If desired, the radio broadcast receivers disclosed can be configured so that they only receive digital FM radio content, for example, if the analog FM broadcast was of no interest and/or if the broadcast was all digital.

Abstract: An apparatus includes a semiconductor package, a radio receiver and a processor. The radio receiver is located in the semiconductor package and includes at least one gain stage. The processor is located in the semiconductor package to execute stored instructions to control the gain stage(s).

Abstract: In one embodiment, the present invention includes an amplifier having an input to receive a radio frequency (RF) signal from an output node of a source. An input stage coupled to the amplifier input may include one or more components to aid in processing of incoming signals. One such component coupled between the source and the input of the amplifier is a coupling capacitor used to maintain a bias voltage of the amplifier at a different potential than a DC voltage of the output node. In certain applications, the amplifier and the coupling capacitor may be integrated on a single substrate.

Abstract: In one embodiment, the present invention includes an amplifier having an input to receive a radio frequency (RF) signal from an output node of a source. An input stage coupled to the amplifier input may include one or more components to aid in processing of incoming signals. One such component coupled between the source and the input of the amplifier is a coupling capacitor used to maintain a bias voltage of the amplifier at a different potential than a DC voltage of the output node. In certain applications, the amplifier and the coupling capacitor may be integrated on a single substrate.

Abstract: A system includes a cellular radio and an FM transmitter that are fabricated in the same semiconductor. The FM transmitter includes at least one mixer, a filter and an antenna tuning network. The mixer(s) translate an intermediate carrier frequency of an input signal to generate a second signal that has an FM carrier frequency. The filter removes spectral energy from the second signal to generate a third signal. The antenna tuning network is separate from the filter and produces a fourth signal to drive an antenna in response to the third signal.

Abstract: An integrated low-IF (low intermediate frequency) terrestrial broadcast receiver and associated method are disclosed that provide an advantageous and cost-efficient solution. The integrated receiver includes a mixer, local oscillator generation circuitry, low-IF conversion circuitry, and DSP circuitry. And the integrated receiver is particularly suited for small, portable devices and the reception of terrestrial audio broadcasts, such as FM and AM terrestrial audio broadcast, in such portable devices.

Abstract: A system and method are disclosed for dynamically selecting high-side injection or low-side injection of local oscillator mixing signals based upon an assessment of signal power within the input signal spectrum that could cause unwanted images in the processed signal. This image rejection assessment provides an advantageous basis upon which to make dynamic high-side versus low-side injection determinations.

Abstract: A receiver for AM and FM broadcast signals is disclosed. FM signals are received from an FM antenna and then processed by receive path circuitry or an FM tuner integrated circuit (IC) to produce audio output signals, such as digital audio output signals. The AM signals are received by an AM antenna and then up-converted using a fixed-clock to a frequency range nearer to the FM signal frequencies. The up-converted AM frequencies are then processed using the receive path circuitry. A multiplexer (MUX) allows for selection of the FM signals or the up-converted AM signals to be passed through for signal processing.

Abstract: On-chip calibration signal generation circuitry is disclosed for filter tuning for radio-frequency communications and associated methods. On-chip circuitry generates a calibration signal that is used to help set a tuning control signal that is received by a tunable front-end filter. In one embodiment, local oscillator (LO) generation circuitry is used to generate the calibration signal. In operation of this embodiment, the LO generation circuitry is tuned to the desired receive channel, or to a frequency at some offset value from the desired receive channel, and the output of the LO generation circuitry is then used as a calibration input signal for a tunable front-end filter. This calibration signal is passed through the receive path circuitry, and the resulting signal is then analyzed to help set a tuning control signal for the tunable front-end filter.

Abstract: An electronic circuit having a circuit stage, such as a switched capacitor stage or a 1-bit digital-to-analog converter and switched capacitor filter, that is loaded with a load impedance employs current feedforward to substantially cancel effects of the load impedance. A circuit includes a circuit stage and a load impedance following and connected to the circuit stage. A current feedforward circuit is connected to the load impedance, substantially cancelling the load impedance to improve linearity of the digital-to-analog converter or switched capacitor filter.

Abstract: A 1-bit discrete time digital-to-analog converter which samples a reference voltage and ground potential onto two charging capacitors during a sample phase of each sampling period, and which transfers the charge on one of the capacitors, as determined by a digital input signal, onto an integrator during a transfer phase of said sampling circuit, draws current from the reference voltages which is independent of the data into the converter. The improvement comprises the addition of at least one phase to each sampling period so that the current drawn from said reference voltage is essentially independent of said digital input signal.

Abstract: The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.

Abstract: A 1-bit discrete time digital-to-analog converter which samples a reference voltage and ground potential onto two charging capacitors during a sample phase of each sampling period, and which transfers the charge on one of the capacitors, as determined by a digital input signal, onto an integrator during a transfer phase of said sampling circuit, draws current from the reference voltages which is independent of the data into the converter. The improvement comprises the addition of at least one phase to each sampling period so that the current drawn from said reference voltage is essentially independent of said digital input signal.

Abstract: A triple cascoded mirror active load includes three transistors (20), (26) and (28) in a first leg and three transistors (22), (30) and (34) in an output leg connected to an output node (18). The first leg receives a current on an input node (14) on the drain of transistor (20). Transistor (20) has the gate thereof connected to the drain of transistor (26) with the gates of transistors (24) and (30) connected together and to a bias voltage. Transistor (20) is mirrored to transistor (22) by connecting the gates thereof together. Similarly, the gates of transistors (28) and (34) are connected together and also to the node (14). In this manner, the node (14) receives a low impedance on the input thereto, whereas the gate of transistor (22) sees a high impedance thereto and with only two transistors, transistors 26 and 28, disposed in a loop as a ratioed cascoded configuration.

Abstract: A modified lossy integrator digital-to-analog converter includes an amplifier (46) that receives an input on a summing node (48) and provides an output on a node (52). A feedback capacitor (50) is disposed across the input and output and has an output switched-capacitor (54) disposed in parallel therewith to passively distribute the charge thereacross. Switches (60) and (66) are operable to control the switching operation of the capacitor (54). Two input switched capacitors (70) and (94) are controlled by associated switches to switch charge onto the summing node (48) in a first clock cycle .phi..sub.2. A one-bit data stream modulates the operation such that either the charge from the capacitor (78) is dumped onto the summing node (48) or the charge from the capacitor (94) is dumped onto the summing node (48). This operation during the .phi..sub.2 cycle provides an integrated output that is slew-limited.