Abstract: A technique to reduce memory bandwidth requirements for image and/or video processing systems is described herein. The technique may include retrieving a plurality of images from a memory, and sequentially processing overlapping subsets of the plurality of images to provide a plurality of output images, wherein the output images are spatially and temporally different. Example implementations may include a processor configured to process input images and to provide output images, a buffer coupled to the processor and configured to store a plurality of input images, and a control unit coupled to the buffer and configured to select subsets of input images from the plurality of images to process for a respective output image, wherein each subset of input images from the plurality of images overlaps with a previous and a subsequent subset of input images from the plurality of images.

Abstract: In a motion compensation engine, a number of blocks are provided for re-ordering motion vector (MV) reference positions prior to fetch. An MV Sort & Group block outputs MVs one at a time to a Decomposer block. The Decomposer block takes each MV and decomposes it into a series of DRAM read commands consisting of DRAM addresses. This rectangular region is divided into pixel words, which correspond to addressable DRAM words. The addresses are then sent to an Overlap Remover block, which comprises a bitmap corresponding to the DRAM addresses sent to it from the Decomposer block. Before a group is received, the bitmap is cleared by setting all coordinates to “0”. Each address received causes the Overlap Remover to set a bit to “1” in the bitmap which corresponds to a relative (x,y) coordinate within a small bounded rectangular region. Addresses received within a group, which are the same as previous addresses, are overlapping addresses and the corresponding bit will simply remain set to “1”.

Abstract: In a motion compensation engine, a number of blocks are provided for re-ordering motion vector (MV) reference positions prior to fetch. An MV Sort & Group block outputs MVs one at a time to a Decomposer block. The Decomposer block takes each MV and decomposes it into a series of DRAM read commands consisting of DRAM addresses. This rectangular region is divided into pixel words, which correspond to addressable DRAM words. The addresses are then sent to an Overlap Remover block, which comprises a bitmap corresponding to the DRAM addresses sent to it from the Decomposer block. Before a group is received, the bitmap is cleared by setting all coordinates to “0”. Each address received causes the Overlap Remover to set a bit to “1” in the bitmap which corresponds to a relative (x,y) coordinate within a small bounded rectangular region. Addresses received within a group, which are the same as previous addresses, are overlapping addresses and the corresponding bit will simply remain set to “1”.