Patents by Inventor Dan Biederman

Dan Biederman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11687264
    Abstract: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Chih-Jen Chang, Brad Burres, Jose Niell, Dan Biederman, Robert Cone, Pat Wang, Kenneth Keels, Patrick Fleming
  • Publication number: 20220116478
    Abstract: Systems and techniques for microservice latency reduction are described herein. A request may be received for execution of a microservice. An execution time may be calculated for the microservice. The execution time may be an estimation of time to complete execution of the microservice. A service level objective (SLO) may be identified. A processing unit of a computing node may be identified for execution of the microservice based on the precise execution time and the SLO. The microservice may be transmitted to the processing unit for instantiation.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Inventors: Dan Biederman, Haichuan Tan, Pradeep Sakhamoori, Gabriel Arrobo Vidal
  • Patent number: 10848430
    Abstract: Various systems and methods for implementing a flexible packet processing mechanism are provided herein. A network interface device for implementing flexible packet processing includes a packet parser to: receive a packet; and determine from analyzing the packet, a corresponding processing element that is used to process the packet; and a coordinator circuit to: determine whether the processing element is active in a computing unit; load the processing element when it is not active; and forward the packet to the processing element.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Dan Biederman, Michael Orr
  • Patent number: 10362149
    Abstract: Various systems and methods for implementing intelligent packet aggregation are provided herein. A network interface device for implementing intelligent packet aggregation including a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics; and a coordinator circuit to: interface with a processing element to determine a current operational state of the processing element; select a queue from the plurality of queues based on the current operational state of the processing element; and forward a number of packets from the selected queue to the processing element.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Dan Biederman, Michael Orr
  • Publication number: 20180191629
    Abstract: Various systems and methods for implementing time-based flexible packet scheduling are provided herein. A network interface device for implementing time-based flexible packet scheduling including a packet parser to: determine from analyzing a packet, a corresponding processing element that is used to process the packet; and store the packet in a queue; and a coordinator circuit to: determine a timing of when the processing element is active in a computing unit; and modify the priority of the packet in the queue based on the timing of when the processing element is active in the computing unit.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Dan Biederman, Michael Orr
  • Publication number: 20180191632
    Abstract: Various systems and methods for implementing flexible packet scheduling are provided herein. A network interface device for implementing flexible packet scheduling includes a packet parser to: receive a packet; determine from analyzing the packet, a corresponding processing element that is used to process the packet; and store the packet in a queue; and a coordinator circuit to: determine whether the processing element is active in a computing unit; and modify the priority of the packet in the queue based on whether the processing element is active in the computing unit.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Dan Biederman, Michael Orr
  • Publication number: 20180191642
    Abstract: Various systems and methods for implementing intelligent packet aggregation are provided herein. A network interface device for implementing intelligent packet aggregation including a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics; and a coordinator circuit to: interface with a processing element to determine a current operational state of the processing element; select a queue from the plurality of queues based on the current operational state of the processing element; and forward a number of packets from the selected queue to the processing element.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Dan Biederman, Michael Orr
  • Publication number: 20180191631
    Abstract: Various systems and methods for implementing a flexible packet processing mechanism are provided herein. A network interface device for implementing flexible packet processing includes a packet parser to: receive a packet; and determine from analyzing the packet, a corresponding processing element that is used to process the packet; and a coordinator circuit to: determine whether the processing element is active in a computing unit; load the processing element when it is not active; and forward the packet to the processing element.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Dan Biederman, MIchael Orr
  • Publication number: 20180152317
    Abstract: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 31, 2018
    Inventors: Chih-Jen Chang, Brad Burres, Jose Niell, Dan Biederman, Robert Cone, Pat Wang, Kenneth Keels, Patrick Fleming