Abstract: Systems, methods, and an article of manufacture for performing serial concatenated decoding are shown and described. The decoding includes monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding and determining whether applying sub-optimal inner decoding would reduce a computational load experienced by a processor performing the serial concatenated decoding when compared to the computation load experienced by the processor when optimal inner decoding is applied.

Abstract: An interface circuit configured to connect between (a) a broadcast receiver tuner and associated circuitry for the receiving and processing of broadcast radio frequency signals, and (b) a general purpose computer device programmed with software demodulation code configured to engage a general purpose processor in signal demodulation functions, the interface circuit comprising: a data interface comprising a packetisation buffer connected to receive (i) digital signal sample data from a signal path of the tuner and associated circuitry and (ii) indications of control settings which are applied to one or more configurable components during taking of the sample data, said packetisation buffer being operable to construct packets comprising blocks of sample data and header information carrying said control settings indications; a control interface configured to receive control instructions from tuner control code running on the general purpose computer device; and a microcontroller operable to receive the control i

Abstract: An interface circuit configured to connect between (a) a broadcast receiver tuner and associated circuitry for the receiving and processing of broadcast radio frequency signals, and (b) a general purpose computer device programmed with software demodulation code configured to engage a general purpose processor in signal demodulation functions, the interface circuit comprising: a data interface comprising a packetisation buffer connected to receive (i) digital signal sample data from a signal path of the tuner and associated circuitry and (ii) indications of control settings which are applied to one or more configurable components during taking of the sample data, said packetisation buffer being operable to construct packets comprising blocks of sample data and header information carrying said control settings indications; a control interface configured to receive control instructions from tuner control code running on the general purpose computer device; and a microcontroller operable to receive the control i

Abstract: A broadcast receiver system comprising: a tuner circuit operable to detect a plurality of modulated radio frequency signals, including TV broadcast signals, and comprising at least one signal path each comprising an analogue mixer and analogue filter circuitry arranged respectively to frequency convert and pre-select received analogue signals; further circuitry comprising an analogue to digital converter and digital filter circuitry; a data interface to a software demodulation module operable to engage a general purpose processor of a computer in data demodulation and decoding functions; a control, interface; and a microcontroller arranged to receive control information from said computer via the control interface.

Abstract: A bridge circuit configured for connection between a tuner circuit capable of receiving broadcast analogue frequencies and a general purpose processor capable of demodulating the received broadcast signal, the circuit comprising: a tuner interface capable of receiving at least one signal component in analogue form from tuner circuitry; an analogue to digital converter connected to receive the analogue signal from the tuner interface and convert it to a digital signal for filtering; a digital filter connected to receive and filter the digital signal; an external digital interface; and a microcontroller arranged to receive control information via said external digital interface, wherein one or more or the analogue to digital converter and the digital filter is provided with a controllably variable clock input.

Abstract: Systems, methods, and an article of manufacture for performing serial concatenated decoding are shown and described. The decoding includes monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding and determining whether applying sub-optimal inner decoding would reduce a computational load experienced by a processor performing the serial concatenated decoding when compared to the computation load experienced by the processor when optimal inner decoding is applied.

Abstract: A system is provided implementing an extremely high speed link allowing selection of either twisted pair (or like media) and fiber media in a single local area network to provide a high speed multimedia local area network. A high speed transmission link for twisted pair, coaxial cable media or the like is provided including a transmitter with a conversion device for receiving fiber optic data interface signals intended to drive a fiber optic data interface and for converting said fiber optic data interface signals into high speed transmission link signals of a form suitable to drive a shielded twisted pair medium. A receiver is provided including reconversion apparatus for regenerating the signal received from the shielded twisted pair medium back to an adequate signal level. The transmitter conversion device includes a buffer cooperating with an equalizer and a filter for forming the high speed transmission link signal.

Abstract: A local area network including at least one hub unit, at least one associated station unit and a wireless communication link between each hub unit and its associated station units. The communication link includes a wireless down-link channel for transferring information from each hub unit to its associated station units and a wireless up-link channel for transferring information from each station unit to its associated hub unit. Communication is conducted in accordance with a combination time division multiplexing and contention based protocol. A synchronized common slotted time frame between each hub unit and its associated station units is imposed by the hub unit.