Abstract: A collision avoidance system and collision avoidance method for a detection bed are described. The collision avoidance system comprises stress sensors for measuring a stress caused by supporting a bed face of the detection bed and outputting stress data; a collector, which is connected with the stress sensors and is configured to collect the stress data output by each of the stress sensors; a judging processor, which is connected with the collector and is configured to judge whether the collected stress data monotonically changes within a preset time; and a controller connected with the judging processor, the controller controlling the bed face of the detection bed so that it stops moving when the judging processor determines that the collected stress data monotonically changes within the preset time.

Abstract: A collision avoidance system and collision avoidance method for a detection bed are described. The collision avoidance system comprises stress sensors for measuring a stress caused by supporting a bed face of the detection bed and outputting stress data; a collector, which is connected with the stress sensors and is configured to collect the stress data output by each of the stress sensors; a judging processor, which is connected with the collector and is configured to judge whether the collected stress data monotonically changes within a preset time; and a controller connected with the judging processor, the controller controlling the bed face of the detection bed so that it stops moving when the judging processor determines that the collected stress data monotonically changes within the preset time.

Abstract: A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture.

Abstract: A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

Abstract: A graphics pipeline includes a plurality of sequentially arranged processing stages which render display pixel data from input primitive object data. The processing stages include at least a texturing stage and a depth test stage, and the depth test stage may be located earlier in the graphics pipeline than the texturing stage.

Abstract: An embedded device is provided which comprises a device memory and hardware entities including a 3D graphics entity. The hardware entities are connected to the device memory, and at least some of the hardware entities perform actions involving access to and use of the device memory. A grid cell value buffer is provided, which is separate from the device memory. The buffer holds data, including buffered grid cell values. Portions of the 3D graphics entity access the buffered grid cell values in the buffer, in lieu of the portions directly accessing the grid cell values in the device memory, for per-grid processing by the portions.

Abstract: A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture.

Abstract: An improved crank structure for bicycle, wherein, a gear plate connector and a pedal connector are installed on two ends of a crank, and there are a first side and a second side extended between the gear plate connector and the pedal connector; there are two pairs of thickness and width perpendicularly and crosswise installed on each of the first side and the second side, and the thicknesses and widths can be measured; the feature is the crank is a non-symmetrical structure. Further, at least one cavity is positioned between the first side and the second side of crank for loosing weight and decreasing cost.