Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.

Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.

Abstract: Apparatus having first and second sets of memory devices commonly connected to receive a first enable signal and a second enable signal, respectively, and a multiplexer connected to receive the first and second enable signals. The multiplexer is configured to connect the first set of memory devices to an output of the apparatus in response to the first enable signal having a first logic level, and to isolate the first set of memory devices from the output in response to the first enable signal having a second logic level different than the first logic level. The multiplexer is further configured to connect the second set of memory devices to the output in response to the second enable signal having the first logic level, and to isolate the second set of memory devices from the output in response to the second enable signal having the second logic level.

Abstract: Apparatus having first and second sets of memory devices commonly connected to receive a first enable signal and a second enable signal, respectively, and a multiplexer connected to receive the first and second enable signals. The multiplexer is configured to connect the first set of memory devices to an output of the apparatus in response to the first enable signal having a first logic level, and to isolate the first set of memory devices from the output in response to the first enable signal having a second logic level different than the first logic level. The multiplexer is further configured to connect the second set of memory devices to the output in response to the second enable signal having the first logic level, and to isolate the second set of memory devices from the output in response to the second enable signal having the second logic level.