Patents by Inventor Dan Froelich

Dan Froelich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reduced pin count interface
    Patent number: 11163717
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • REDUCED PIN COUNT INTERFACE
    Publication number: 20210056067
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Application
    Filed: July 6, 2020
    Publication date: February 25, 2021
    Applicant: Intel Corporation
    Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • Reduced pin count interface
    Patent number: 10198394
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • REDUCED PIN COUNT INTERFACE
    Publication number: 20170344512
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Application
    Filed: October 1, 2016
    Publication date: November 30, 2017
    Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • Two-window recovered clock jitter analysis
    Publication number: 20060133469
    Abstract: Jitter in a clock signal is evaluated. A period of the clock is recovered from the clock signal in a first window, and the clock signal is evaluated for jitter within a second window that is smaller than the first window and located within the first window.
    Type: Application
    Filed: December 31, 2003
    Publication date: June 22, 2006
    Inventors: Dan Froelich, Per Fornberg, Andrew Volk