Abstract: Systems, methods, and devices for wireless communication that support mechanisms for identifying hyper frame number (HFN) desynchronization conditions and/or for triggering HFN resynchronization in a wireless communication system. In aspects, an HFN desynchronization condition is identified based on Ethernet frame validation. For example, aspects of the present disclosure provide mechanisms for validating and Ethernet frame. An HFN desynchronization condition is identified or detected when an Ethernet frame is determined to be corrupt based on the Ethernet frame validation in accordance with aspects herein. In some aspects, such as in Ethernet header compression (EHC) protocol implementations, an HFN desynchronization condition may be identified based on a determination that a deciphered context identification (CID) is not a valid CID (e.g., is not a CID in a set of valid CIDs).

Abstract: Systems, methods, and devices for wireless communication that support mechanisms for identifying hyper frame number (HFN) desynchronization conditions and/or for triggering HFN resynchronization in a wireless communication system. In aspects, an HFN desynchronization condition is identified based on Ethernet frame validation. For example, aspects of the present disclosure provide mechanisms for validating and Ethernet frame. An HFN desynchronization condition is identified or detected when an Ethernet frame is determined to be corrupt based on the Ethernet frame validation in accordance with aspects herein. In some aspects, such as in Ethernet header compression (EHC) protocol implementations, an HFN desynchronization condition may be identified based on a determination that a deciphered context identification (CID) is not a valid CID (e.g., is not a CID in a set of valid CIDs).

Abstract: This disclosure provides a method, apparatus, and computer-readable medium for wireless communication at a modem, comprising receiving, via an interface with a host, an internet protocol (IP) packet including a first transport protocol header and a first IP header. The IP packet has a size greater than a maximum transport unit (MTU) size allowable for each packet transmitted over a communication link. The modem segments the IP packet into a plurality of segments based on a segment size indicated by a segmentation policy. Each segment includes a respective derived segment transport protocol header and a respective derived segment IP header derived from the IP packet. Each of these derived headers includes at least one field based on the segmentation policy, and each of the segment transport protocol headers includes a checksum for the respective segment. Additionally, the modem transmits the plurality of segments over the communication link.

Abstract: Various aspects of the present disclosure generally relate to wired and/or wireless communication. In some aspects, a device may receive a plurality of data packets at a modem of the device. The device may group, at the modem of the device, payloads of a first subset of the plurality of data packets into a container. The device may transfer, to a processor of the device and using the modem, the container via a first interface channel. The device may transfer, to the processor and using the modem, a second subset of the plurality of data packets via a second interface channel. Numerous other aspects are provided.

Abstract: Various aspects of the present disclosure generally relate to wired and/or wireless communication. In some aspects, a device may receive a plurality of data packets at a modem of the device. The device may group, at the modem of the device, payloads of a first subset of the plurality of data packets into a container. The device may transfer, to a processor of the device and using the modem, the container via a first interface channel. The device may transfer, to the processor and using the modem, a second subset of the plurality of data packets via a second interface channel. Numerous other aspects are provided.

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.

Abstract: A virtualized Internet Protocol (IP) packet processing system is provided. In this regard, in one aspect, a computing circuit for processing IP packets is shared among a plurality of virtual clients. The computing circuit includes a plurality of hardware functional blocks each configured to perform a predefined IP packet processing function. In another aspect, a virtual channel is created for each of the virtual clients and assigned with one or more of the hardware functional blocks. In this regard, IP packets associated with each of the virtual clients may be processed by respective assigned hardware functional blocks based on a specified processing sequence. By sharing the computing circuit among the virtual clients and assigning respective hardware functional blocks to each virtual client, it is possible to optimize processing efficiency of the computing circuit, thus improving throughput, latency, and power consumption of the virtualized IP packet processing system.

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.