Abstract: Tensor transformation includes obtaining an input tensor having a first data-layout format and elements of a first data type, and reformatting the input tensor to provide an output tensor having a second data-layout format and elements of a second data type, where the second data-layout is different from the first data-layout format and the second data type is different from the first data type. Optionally, the reformatting includes element quantization on input elements of the input tensor, where the element quantization performed on an input element of the input tensor includes converting the input element to an output element, of the second data type, as an element of the output tensor, using the scale value to scale to the input element, the offset value to apply an offset, and the clip maximum and clip minimum values to enforce a maximum value and a minimum value for the output element.

Abstract: Dimension control in tensor multiplication includes obtaining first and second input tensors for matrix multiplication, obtaining a dimension control indicator that indicates a first dimension for the first input tensor to use as a common dimension for the matrix multiplication and indicates a second dimension for the second input tensor to use as the common dimension for the matrix multiplication, and performing the matrix multiplication to obtain one or more results, where performing the matrix multiplication includes selecting at least one vector of the first input tensor based on the first dimension indicated by the dimension control indicator and selecting at least one vector of the second input tensor based on the second dimension indicated by the dimension control indicator.

Abstract: Tensor multiplication with quantization includes obtaining first and second input tensors, obtaining elements of a selected data type based on elements of the first input tensor and elements of the second input tensor, performing matrix multiplication on the elements of the selected data type, the matrix multiplication including performing quantization of intermediate results, and the quantization scaling the intermediate results to provide scaled results of the matrix multiplication, and generating output elements, for an output tensor, using the scaled results. Optional additional quantization is performed on elements of an input tensor to provide at least some of the elements of the selected data type for the matrix multiplication.

Abstract: Tensor processing includes obtaining an input tensor, the input tensor including a dimension of index size n, determining an element count, c, based on an indicator, the indicator specified by the instruction, and the element count specifying a number of vector elements on which to perform an artificial intelligence function, obtaining an input vector, of the input tensor, of size n, and performing the artificial intelligence function, the performing the artificial intelligence function including performing the artificial intelligence function on a first c number of elements of the input vector to provide a corresponding c number of elements of an output vector of index size n of an output tensor.

Abstract: Tensor processing with broadcasting includes obtaining a first input tensor, the first input tensor including a dimension of index size one, and performing an artificial intelligence processing operation using the first input tensor and a second input tensor to obtain results, the second input tensor including a dimension of index size greater than one, where performing the artificial intelligence processing operation includes broadcasting the dimension of index size one of the first input tensor to match the dimension of index size greater than one of the second input tensor.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: A single architected instruction to move data is executed. The executing includes moving data of a specified length from a source location to a destination location in a right-to-left sequence to provide a predictable result. A predictable result is provided, even though a portion of the destination location is contained within the source location from which the data is being moved.

Abstract: A single architected instruction to move data is executed. The executing includes moving data of a specified length from a source location to a destination location in a right-to-left sequence to provide a predictable result. A predictable result is provided, even though a portion of the destination location is contained within the source location from which the data is being moved.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.

Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.

Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.

Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.

Abstract: A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation.

Abstract: An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code table.

Abstract: The updating of components of storage keys is managed. A control program indicates whether the updating of selected components of a storage key can be bypassed. If the updating of the selected components can be bypassed, then depending on the circumstances, an update of the storage key may not need to be performed, saving on quiesce operations. The likelihood that the updating of a storage key can be bypassed is enhanced by selecting a block of storage, along with its associated storage key, from a designated queue or designated region of a queue.