Abstract: A portable, independent thermoelectric temperature regulated system for providing active cooling to one or more payloads. The system includes a thermally insulated housing, one or more thermoelectric converters embedded in the thermally insulated housing, and a power source. The system may include one or more optional payload containers. Multiple payload containers may be used in the same housing. The system includes a control circuit for managing temperature of the payload(s) based on user selections. The housing may be hard or soft, and the multiple payload containers may be maintained at different temperatures. Optional phase change materials may be included that may be charged by the active thermoelectric converter discharged as a source of passive cooling or heating.

Abstract: A portable, independent thermoelectric temperature regulated system for providing active cooling to one or more payloads. The system includes a thermally insulated housing, one or more thermoelectric converters embedded in the thermally insulated housing, and a power source. The system may include one or more optional payload containers. Multiple payload containers may be used in the same housing. The system includes a control circuit for managing temperature of the payload(s) based on user selections. The housing may be hard or soft, and the multiple payload containers may be maintained at different temperatures. Optional phase change materials may be included that may be charged by the active thermoelectric converter discharged as a source of passive cooling or heating.

Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture.

Abstract: The present disclosure relates to semiconductor devices and the teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET). Some embodiments may include a power MOSFET with transistor cells, each cell comprising a source and a drain region; a first dielectric layer disposed atop the transistor cells; a silicon rich oxide layer on the first dielectric layer; grooves through the multi-layered dielectric, each groove above a respective source or drain region and filled with a conductive material; a second dielectric layer atop the multi-layered dielectric; openings in the second dielectric layer, each opening exposing a contact area of one of the plurality of grooves; and a metal layer disposed atop the second dielectric layer and filling the openings. The metal layer may form at least one drain metal wire and at least one source metal wire. The at least one drain metal wire may connect two drain regions through respective grooves.

Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture.

Abstract: A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.

Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.