Abstract: In a computer system the instruction decoding unit for translating program instructions to microcode instructions operates dynamically. Thus the unit receives state signals indicating the state of the computer, such as a trace enabling signal, influencing the translation process in the instruction decoding unit. These state signals are added to the operation code of the program instruction to be decoded, the operation code of the program instruction thus being extended and used as input to a translating table, the extended operation code of the program instruction being taken as an address of a field in the table. The addresses and thus the contents of the fields addressed for the same operation code of a program instruction can then be different for different values of the state signals. Thus generally, the state signals cause the instruction decoder to change its translating algorithm so that the decoder can decode an operation code differently depending on the state which the signals adopt.

Abstract: When decoding instructions of a program to be executed in a central processing unit comprising pipelining facilities for fast instruction decoding, part of the decoding is executed or the decoding in pipelining units is prepared in a remapping unit during loading a program into a program or primary memory used by the central processor, the remapping or predecoding operation resulting in operation codes which can be very rapidly interpreted by the pipelining units of the central processor. Thus, the operation code field of an instruction is changed to include information on e.g., instruction length, jumps, parameters, etc., this information indicating the instruction length, whether it is a jump instruction or has a parameter etc. respectively, in a direct way that allows the use of simple combinatorial circuits in the pipelining units.

Abstract: An arrangement and a method provide instruction processing. Instructions are delivered to a multi-stage pipeline arrangement from at least one instruction source. A storing arrangement stores jump address information for jump instructions. The storing arrangement includes at least one FIFO-register. The conditional jump target address information is stored in the FIFO-register while at least the jump instructions are stored in the pipeline arrangement. The jump target address information is delivered from the FIFO-register in such a way that substantially sequential and continuous prefetching of the instructions is enabled irrespective of the number of conditional jumps and irrespective of whether the jumps are taken or not.