Patents by Inventor Dan L. Cossentine

Dan L. Cossentine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system
    Patent number: 6846149
    Abstract: A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: January 25, 2005
    Assignee: Aviza Technology, Inc.
    Inventors: Richard N. Savage, Frank S. Menagh, Helder R. Carvalheira, Philip A. Troiani, Dan L. Cossentine, Eric R. Vaughan, Bruce E. Mayer
  • Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system
    Patent number: 6610150
    Abstract: A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: August 26, 2003
    Assignee: ASML US, Inc.
    Inventors: Richard N. Savage, Frank S. Menagh, Helder R. Carvalheira, Philip A. Troiani, Dan L. Cossentine, Eric R. Vaughan, Bruce E. Mayer
  • Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system
    Publication number: 20020033136
    Abstract: A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.
    Type: Application
    Filed: November 27, 2001
    Publication date: March 21, 2002
    Applicant: Silicon Valley Group, Thermal Systems LLC.
    Inventors: Richard N. Savage, Frank S. Menagh, Helder R. Carvalheira, Philip A. Troiani, Dan L. Cossentine, Eric R. Vaughan, Bruce E. Mayer
  • Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system
    Publication number: 20010010950
    Abstract: A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.
    Type: Application
    Filed: January 22, 2001
    Publication date: August 2, 2001
    Applicant: Silicon Valley Group Thermal Systems LLC
    Inventors: Richard N. Savage, Frank S. Menagh, Helder R. Carvalheria, Philip A. Troiani, Dan L. Cossentine, Eric R. Vaughan, Bruce E. Mayer