Abstract: The present invention relates to an apparatus and method for enhancing the differential signaling speed performance of a PCI bus within a data processing system. In particular it involves the connectors employed with PCI bus architecture. The present invention involves providing improved connectors employed in a PCI bus architecture. These are Split Pin and Split Via connectors which provide significantly higher frequency and higher frequency capability to the board level.

Abstract: A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. Each bus to bus bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information.