Patents by Inventor Dan Mauricio Bruck

Dan Mauricio Bruck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5963076
    Abstract: In a circuit (10), a first N-FET (N1) and a second N-FET (N2) are coupled serially between a node (15) and ground (93). The circuit (10) accommodates a first excursion (85) of a first signal (IN) at the gates of the first N-FET (N1) which is higher than the maximum allowable drain-source voltage for N-FETs. The voltage of a second signal (OUT) between the node (15) and ground (93) is distributed across the first and the second N-FETs (N1, N2). The gate voltage of the second N-FET (N2) is not constant, but controlled by a control circuit (20) receiving signals the first signal (IN) and, optionally, the second signal (OUT). With the variation of the gate voltage for the second N-FET (N2), the size of both transistors (N1, N2) can be reduced and the fall time (T.sub.F) of the second signal (OUT) can be reduced.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: October 5, 1999
    Assignee: Motorola, Inc.
    Inventors: Joseph Shor, Mark Yosefin, Dan Mauricio Bruck