Abstract: A Class-D switching amplifier (30, 40) having a ternary mode of operation. Signal processing (21, 22) is provided to eliminate the potential of crosstalk within one channel by introducing a time delay into the system. A susceptible crosstalk point is moved away from a zero-crossing point to a higher power level, which is advantageous in low-end audio applications. A time delay is introduced to one ramp signal (RAMPB) in the first implementation (30), and an in-sync generator (42) is utilized in another implementation (40) using offset switching in the comparitors (40, 42) to create the time delay (&Dgr;t).

Abstract: A gain stage circuit includes a first transistor Q.sub.3 having a control node coupled to a bias node V.sub.B1 ; a second transistor Q.sub.2 having a control node coupled to the bias node V.sub.B1 ; a third transistor Q.sub.1 coupled in series with the second transistor Q.sub.2 and having a control node coupled to an input node V.sub.IN ; a fourth transistor Q.sub.5 matched to the second transistor Q.sub.2 and having a control node coupled to the bias node V.sub.B1 ; a current subtracting circuit 22 coupled to the second and fourth transistors Q.sub.2 and Q.sub.5 ; and a quiet current generator 20 coupled to the current subtracting circuit 22, the current subtracting circuit 22 subtracts a current in the fourth transistor Q.sub.5 from a quiet current in the quiet current generator 20.