Patents by Inventor Dan Okamoto

Dan Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11735435
    Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: August 22, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dan Okamoto, Hiroyuki Sada
  • Publication number: 20200251352
    Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Dan Okamoto, Hiroyuki Sada
  • Patent number: 10665475
    Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dan Okamoto, Hiroyuki Sada
  • Publication number: 20170352609
    Abstract: A leadframe wherein the outer sidewalls of the leadframe that are exposed by sawing during singulation are comprised of greater than 50% solder. A leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised of greater than 50% solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised primarily of solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised entirely of solder.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Inventor: Dan Okamoto
  • Publication number: 20170271244
    Abstract: A leadframe wherein the outer sidewalls of the leadframe that are exposed by sawing during singulation are comprised of greater than 50% solder. A leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised of greater than 50% solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised primarily of solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised entirely of solder.
    Type: Application
    Filed: March 21, 2016
    Publication date: September 21, 2017
    Inventor: Dan Okamoto
  • Patent number: 9536753
    Abstract: A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: January 3, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yohei Koto, Kazunori Hayata, Dan Okamoto
  • Publication number: 20160315036
    Abstract: A dual transistor device includes a first transistor having a first drain, a first gate, and first source and a second transistor having a second drain, a second gate, and a second source. A first terminal is substantially flat and has a first surface. The first source is located adjacent a first portion of the first surface and is electrically coupled to the first terminal. The second drain is located adjacent a second portion of the first surface and is electrically coupled to the first terminal.
    Type: Application
    Filed: April 24, 2015
    Publication date: October 27, 2016
    Inventors: Makoto Shibuya, Dan Okamoto
  • Publication number: 20160307831
    Abstract: A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventor: Dan Okamoto
  • Patent number: 9379087
    Abstract: A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: June 28, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dan Okamoto
  • Publication number: 20160133599
    Abstract: A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventor: Dan Okamoto
  • Publication number: 20160099226
    Abstract: A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 7, 2016
    Inventors: Yohei KOTO, Kazunori HAYATA, Dan OKAMOTO
  • Publication number: 20150364373
    Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.
    Type: Application
    Filed: June 11, 2014
    Publication date: December 17, 2015
    Inventors: Dan Okamoto, Hiroyuki Sada
  • Publication number: 20150348881
    Abstract: A method of making a QFD package including providing a clip and coating at least a first end portion of the clip with solder paste.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dan Okamoto
  • Publication number: 20150340324
    Abstract: A semiconductor package assembly includes a substrate having an upper surface with a die attachment region thereon. A layer of die attachment material is positioned on top of the die attachment region. The semiconductor package assembly also includes an integrated circuit (“IC”) die. The die has a top portion including a laterally extending top wall surface and a plurality of generally vertically extending wall surfaces extending downwardly from the top wall surface. The die has a metallized bottom portion. The bottom portion has at least two metallized laterally extending wall surfaces and a plurality of metallized generally vertically extending connecting surfaces that connect the metallized laterally extending surfaces of the bottom portion. The layer of die attachment material interfaces with one or both of the metallized laterally extending surfaces and the plurality of metallized generally vertically extending connecting wall surfaces.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 26, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Kazunori Hayata, Yohei Koto, Dan Okamoto
  • Publication number: 20130264836
    Abstract: A system comprises a collet is configured for holding a die surface against the bearing surface and for simultaneously pushing outward on the center region of the die so held.
    Type: Application
    Filed: May 21, 2013
    Publication date: October 10, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Dan OKAMOTO, Seiichi YAMASAKI
  • Patent number: 8465619
    Abstract: Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: June 18, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Dan Okamoto, Seiichi Yamasaki
  • Publication number: 20100289159
    Abstract: Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface.
    Type: Application
    Filed: July 28, 2010
    Publication date: November 18, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dan OKAMOTO, Seiichi YAMASAKI
  • Patent number: 7790507
    Abstract: Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface.
    Type: Grant
    Filed: March 24, 2007
    Date of Patent: September 7, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Dan Okamoto, Seiichi Yamasaki
  • Publication number: 20080233680
    Abstract: Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface.
    Type: Application
    Filed: March 24, 2007
    Publication date: September 25, 2008
    Inventors: Dan Okamoto, Seiichi Yamasaki
  • Publication number: 20070037376
    Abstract: According to one embodiment of the invention, a method of assembling a package has been provided that includes coupling a plurality of solder balls to a first surface of a substrate. At least one of the plurality of solder balls is in communication with a trace that extends from the first surface of the substrate to a second surface of the substrate. A removable laminate is disposed over the plurality of solder balls. A die is coupled to the second surface of the substrate. Communication between the die and the at least one of the plurality of solder balls is established through the trace by wire bonding the die to the trace. A mold compound is disposed around the die. The removable laminate may then be removed to expose the plurality of solder balls.
    Type: Application
    Filed: August 11, 2005
    Publication date: February 15, 2007
    Inventor: Dan Okamoto