Abstract: For fault testing in a digital system, a processor unit is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyze is activated and the processor unit generates a set of stimuli, influencing the appropriate logical units. The output response analyzer collects responses to the stimuli at different nodes in the digital system and creates signatures from them. The signals are verified and if a fault is noticed, this error is noticed. The present state of the processor and other logical units are stored in a storage device prior to the test and recovered after the testing is finished. This fault testing can be performed both at chip and board levels, and on systems with several units.

Abstract: Loops in program code are avoided by generating instructions for controlling a processor. A first template instruction is stored, and a predetermined number of instructions may be generated, wherein each generated instruction is based on the first template instruction. The processor may be alternatively supplied with the generated instructions or with instructions received from an alternative instruction source. A substitute address field may be stored, and the step of generating each instruction may include substituting the substitute address field in place of an address field in the first template instruction. The stored substitute address field may be adjusted after generating each instruction. The step substituting the substitute address field in place of an address field in the first template instruction may be performed only if a substitution control signal is asserted.