Abstract: A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.

Abstract: A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.

Abstract: A protection circuit with a positive field effect transistor coupled to a power source, a negative field effect transistor connected to a pass-gate and a circuit ground, a circuit input terminal, a multi-level source of protection voltage coupled to an external circuit and at least three additional field effect transistors. A drain of the negative field effect transistor couples to a gate of the positive field effect transistor. When the circuit input terminal is low the pass-gate is on; when the circuit input terminal is high the pass-gate is off. Embodiments of the invention also include stacks of three or more field effect transistors.

Abstract: A protection circuit with a positive field effect transistor coupled to a power source, a negative field effect transistor connected to a pass-gate and a circuit ground, a circuit input terminal, a multi-level source of protection voltage coupled to an external circuit and at least three additional field effect transistors. A drain of the negative field effect transistor couples to a gate of the positive field effect transistor. When the circuit input terminal is low the pass-gate is on; when the circuit input terminal is high the pass-gate is off. Embodiments of the invention also include stacks of three or more field effect transistors.