Patents by Inventor Dan R. Kaiser

Dan R. Kaiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, method, and computer program product for simulating a mixed signal circuit design
    Patent number: 8949100
    Abstract: The present disclosure relates to a computer-implemented method for simulating an analog and mixed-signal circuit design having a digital circuit segment connected to an analog circuit segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the digital circuit segment and the analog circuit segment. The method may further include splitting the digital circuit segment into a plurality of transistor network models to provide for bidirectional transfer of data between the analog circuit segment and the digital circuit segment.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: February 3, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: William S. Cranston, Junwei Hou, Dan R. Kaiser, Aaron Mitchell Spratt
  • Predictive event scheduling in an iterative resolution network
    Patent number: 7870518
    Abstract: A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is configured to receive data from an input. Each enabling element is associated with a resolution device. Enabling elements that are associated with resolution devices that are connected to nodes that are configured to receive input data are activated, thereby enabling certain resolution devices. The enabled resolution devices are executed using data in the nodes that are connected to the enabled resolution devices. Iterations of executing resolution devices are performed until stable node values are determined.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: January 11, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventor: Dan R. Kaiser
  • Predictive event scheduling in an iterative tran resolution network
    Patent number: 7251796
    Abstract: A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is configured to receive data from an input. Each enabling element is associated with a resolution device. Enabling elements that are associated with resolution devices that are connected to nodes that are configured to receive input data are activated, thereby enabling certain resolution devices. The enabled resolution devices are executed using data in the nodes that are connected to the enabled resolution devices. Iterations of executing resolution devices are performed until stable node values are determined.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: July 31, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventor: Dan R. Kaiser