Abstract: A method, system, and computer program product for reducing power consumption in a display area of an electronic device is provided. The method includes selecting a first window within the display area to be highlighted using a first input command of a user; locating the first window in the display area; and reducing power to at least portions of the display area not corresponding to the first window.

Abstract: Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed.

Abstract: Disclosed is method and chaos circuit for a random number generator comprising: a differential sample and hold circuit portion having a first and a second differential signal input and a first and a second differential signal output, a differential non-linear discriminator circuit portion that applies a differential discrimination function upon the first and the second differential signal output and outputs a first and a second discriminated signal, where the first and the second discriminated signals are also coupled to the first and the second differential signal inputs via a first and a second loop feedback.

Abstract: A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing an appropriate component from the function. Approximations of clock gating functions expressed in conjunctive normal form are performed by removing a clause from the function. Approximations of clock gating functions expressed in disjunctive normal form are performed by removing a literal from a clause in the function.

Abstract: A method, system, and computer program product for reducing power consumption in a display area of an electronic device is provided.

Abstract: A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing an appropriate component from the function. Approximations of clock gating functions expressed in conjunctive normal form are performed by removing a clause from the function. Approximations of clock gating functions expressed in disjunctive normal form are performed by removing a literal from a clause in the function.

Abstract: Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed.

Abstract: Disclosed is method and chaos circuit for a random number generator comprising: a differential sample and hold circuit portion having a first and a second differential signal input and a first and a second differential signal output, a differential non-linear discriminator circuit portion that applies a differential discrimination function upon the first and the second differential signal output and outputs a first and a second discriminated signal, where the first and the second discriminated signals are also coupled to the first and the second differential signal inputs via a first and a second loop feedback.

Abstract: A method for encoding a data mask that consists of a given total number of bits and includes a selected group of contiguous bits within the total number, the selected group having a left end and a right end. The method includes dividing the data mask into a plurality of segments, and representing the segments by respective segment codes, each code indicating whether the bits in the respective segment fall entirely outside the selected group, entirely within the selected group, or include the left end or the right end of the group. The segment codes are combined so as to generate a mask code, which can be decoded to reconstruct the data mask.

Abstract: A method for encoding a data mask that consists of a given total number of bits and includes a selected group of contiguous bits within the total number, the selected group having a left end and a right end. The method includes dividing the data mask into a plurality of segments, and representing the segments by respective segment codes, each code indicating whether the bits in the respective segment fall entirely outside the selected group, entirely within the selected group, or include the left end or the right end of the group. The segment codes are combined so as to generate a mask code, which can be decoded to reconstruct the data mask.