Patents by Inventor Dan Ratchen

Dan Ratchen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8977917
    Abstract: In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 10, 2015
    Assignee: Lattice Semiconductor Corporation
    Inventors: Wei Han, Zheng Chen, Eric Lee, Jie Qin, Shankar Durgamahanthi, Kanad Chakraborty, Dan Ratchen
  • Publication number: 20140136914
    Abstract: In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.
    Type: Application
    Filed: April 8, 2013
    Publication date: May 15, 2014
    Applicant: Lattice Semiconductor Corporation
    Inventors: Wei Han, Zheng Chen, Eric Lee, Jie Qin, Shankar Durgamahanthi, Kanad Chakraborty, Dan Ratchen