Abstract: A circuit and method for correcting erroneous data in memory for pipelined reads. A memory controller includes a control unit, a storage unit and an error detection and correction unit. The control unit is configured to read data including an associated error correction code from a memory subsystem in response to a memory read request. The error detection and correction unit is coupled to receive the data and configured to determine whether an error exists in that data based upon the associated error correction code. The control unit is configured to store an indication in the storage unit that the data corresponding to the memory read request is erroneous. The control unit is further configured to detect the indication in the storage unit and to responsively perform a subsequent read of the data from the memory subsystem and to write a corrected version of the data back to the memory subsystem.

Abstract: A computer system may include several caches that are each coupled to receive data from a shared memory. A cache coherency mechanism may be configured to receive a cache fill request, and in response, to send a probe to determine whether any of the other caches contain a copy of the requested data. Some time after sending the probe, the cache controller may provide a speculative response to the cache fill request to the requesting device. By delaying providing the speculative response until some time after the probes are sent, it may become more likely that the responses to the probes will be received in time to validate the speculative response.

Abstract: An electronic system and method are presented for the implementation of functional redundancy checking (FRC) by comparing “signatures” produced by two different electronic devices, for example central processing units (CPUs). The signatures include a relatively small number of signals which reflect an internal state of each CPU. The electronic system includes a first and second CPU. Each CPU is configured to execute instructions and produce output signals. The first and second CPUs are preferably identical and execute instructions simultaneously such that their internal states and produced output signals should be the same at any given time. Each CPU includes a signature generator for generating the signature. The electronic system also includes a compare unit coupled to receive the signatures. The compare unit compares the signatures and produces an error signal if the signatures are not identical. The electronic system may be a computer system, further including a system bus and chip set logic.

Abstract: A method and system for determining the sequence of execution of instructions in a computer under test using trace data generated upon execution of certain ones of the instructions. In one embodiment, the method comprises locating an initial entry in the trace data and scanning the instructions in program order beginning with an instruction indicated by the initial entry. When a branch instruction is encountered, the trace data is examined to determine the subsequently executed instruction. If the branch is unconditional, a corresponding address entry in the trace data indicates the address of the next instruction. If the branch is conditional, a corresponding bitmap entry in the trace data contains a bit which indicates whether the branch was taken. From this bit and the instructions themselves, the next instruction is determined.

Abstract: A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.

Abstract: An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed.

Abstract: A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central interrupt controller, random access memory, and at least one processor interface. The central interrupt controller systematically selects interrupt requests from the interrupt request interface. Information associated with each interrupt request is stored in the random access memory. The central interrupt controller access the information in the random access memory and uses the information and the state of the currently selected interrupt request to determine a next state for the currently selected interrupt request. The information is passed on to the processor interface to determine when and if the interrupt request should issue to one of the CPUs.

Abstract: A programmable interrupt controller for use in a multiprocessing environment that can support a serial bus to send interrupt information to the processors. The interrupt serial bus has a data line to drive all the interrupt information to all the processors and a clock line to synchronize edges for the data stream. A third line, normally tri-stated, may be used to provide a parity error indication for the serial bus. The serial data includes a processor identification, a pin identification and state information. As the programmable interrupt controller sends the interrupt data on the serial bus, all the processors clock the data and check parity. If a processor finds a parity error, it drives the parity error indication low so that the information may be transmitted again. No processor will execute the command contained in the serial message before the time has elapsed for any of the processors to report a parity error.

Abstract: A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An unique interrupt identification code is assigned to each interrupt request and used to reference information in the storage device associated with each interrupt request. The interrupt request interface uses the unique interrupt identification code to access the information for each interrupt request and determine if the interrupt request should proceed to one of the processor interfaces. The processor interface uses the unique interrupt identification code to access the information in order to determine if and when the interrupt request should issue to one of the CPUs.

Abstract: A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity checker monitors the state of each interrupt request as it is processed through the interrupt controller. The interrupt request is canceled if the interrupt request becomes invalid. Alternatively, the programmable interrupt controller issues a spurious interrupt vector if the interrupt request becomes invalid after a CPU has responded.

Abstract: A computer system is disclosed for selectively invalidating the contents of cache memory in response to the removal, modification, or disabling of system resources, such as for example, an external memory device. The computer system includes an interface unit which defines an address window for the particular system resource. The address window is implemented through the use of a lower address register and an upper address register, which are loaded in response to a lower and upper enable address signal. An upper comparator compares each tag address with the upper address register value, and a lower comparator compares each tag address with the lower address register value. If the tag address falls within the window, it is flushed by the generation of appropriate control signal. In an alternative embodiment, the present invention can be implemented through software by instructions in microcode.

Abstract: An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed.

Abstract: A computer system is provided that includes a microprocessor core having an ICE interrupt line to support an in-circuit emulation mode of the computer system. An interrupt control unit coupled to the ICE interrupt line of the microprocessor core, controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. During normal operation, the microprocessor core executes code out of a "normal" memory region of a system memory coupled to the memory control unit. If the debug interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, causing the microprocessor core to read an ICE vector from the system memory and to thereafter execute ICE code.

Abstract: An integrated processor is provided that includes a CPU core, a local bus coupled to the CPU core, and a variety of peripheral such as a memory controller, a direct memory access controller, and an interrupt controller coupled to the local bus. A bus interface unit is further provided to interface between the CPU local bus and a PCI standard multiplexed peripheral bus. The CPU core, the memory controller, the direct memory access controller, the interrupt controller, and the bus interface unit are all incorporated on a common integrated circuit chip. A local bus control unit is further provided that is capable of generating a loading signal and an address strobe signal synchronously with certain bus cycles that are executed on the PCI bus. The local bus control unit allows external peripheral devices that are compatible with the CPU local bus protocols to be connected through the PCI bus.

Abstract: A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer.

Abstract: A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The lower two order bits of the address value are encoded to provide byte lane information to a peripheral device during the I.backslash.O access cycle. The peripheral device responsively receives or provides data at the specified byte lane. As a result, peripheral devices that may be connected to the local bus will not respond to the I/O access cycle, while encoded byte lane information is provided to the desired peripheral device without requiring dedicated byte select lines.

Abstract: An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required.

Abstract: A clock source selector provides at least one set of clock signals selected from a plurality of clock sources and a synchronized transition from an old clock source to a new clock source. The clock source selector includes a gate having an output for providing the clock signals, a selector coupled between the plurality of clock sources and the gate for providing the gate with clock signals from selected ones of the clock sources responsive to selection signals, a detector for detecting a change in the selection signals from an old clock source to a new clock source, and a synchronizing circuit responsive to the detector for disabling the gate in synchronism with the old clock source and thereafter enabling the gate in synchronism with the new clock source.