Abstract: A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.

Abstract: An address decoder for a source node in a multi-chip system is disclosed, which can perform parallel decoding steps to determine whether a transaction from the source node is addressed to a target node in a local integrated circuit (IC) or a remote IC, and whether the source node is allowed to access that target node. Based on the outcome of both the decoding steps, the transaction can be either blocked by the address decoder, or routed to the target node. If the transaction is addressed to the remote IC, but the source node is not allowed to access the target node on the remote IC, the transaction can be terminated by the address decoder in the local IC.