Abstract: A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.

Abstract: A system for accessing memory, comprising: transformation circuitry configured to: receive a memory access request; access a transformation mode value associated with the memory access request and indicative of an address transformation function; apply the address transformation function, indicated by the transformation mode value, to a memory address of the memory access request to compute a transformed memory address; and generate a new memory access request using the memory access request and the transformed memory address; and at least one memory area configured to serve the new memory access request according to the transformed memory address.

Abstract: A method for executing a software program, comprising: identifying in a program a plurality of host threads, each for performing some of a plurality of parallel sub-tasks of a task; and for each of the host threads: generating device threads, each associated with the host thread, each for one of the parallel tasks associated thereof; generating a parent thread associated with the host thread for communicating with the device threads; configuring a host processing circuitry to execute the parent thread; and configuring at least one other processing circuitry to execute in parallel the device threads while the host processing circuitry executes the parent thread; and for at least one of the host threads: receiving by the parent thread a value from the at least one other processing circuitry, the value generated when executing at least one of the device threads associated with the at least one host thread.

Abstract: A system for managing cache coherency comprises memory areas, processing cores, cache nodes each associated with at least one of the processing cores, and a hardware processor configured to: for each of the memory areas: cluster the processing cores into clusters according to memory access metrics in relation to the memory area; and for each of the clusters, associate the memory area with a caching scheme; and configure the processing cores to: receive from a first core a memory access command comprising a memory address associated with a memory area, where the first core is a member of a first cluster for the memory area; compute a determination of a target cache node according to the memory access command, where the target cache node is associated with a second core; and access the memory area according to the caching scheme associated with the memory area for the first cluster.

Abstract: A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.

Abstract: A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.

Abstract: There is provided a memory, comprising: issuing an allocation operation for allocation of a region of a memory by a first process of a plurality of first processes executed in parallel on a first processor, sending a message to a second processor indicating the allocation of the region of the pool of the memory, issuing a free operation for release of the allocated region of the pool of the memory by a second process of a plurality of second processes executed in parallel on a second processor, and releasing, by the first processor, the allocated region of the pool of the memory as indicated in the free operation, wherein a same region of memory is allocated by the first process and released by the second process, wherein the first processes are concurrently attempting to issue the allocation operation and the second processes are concurrently attempting to issue the free operation.

Abstract: There is provided a computer implemented method of allocation of memory, comprising: issuing an allocation operation for allocation of a region of a pool of a memory by a first process executed on a first processor, sending a message to a second processor indicating the allocation of the region of the pool of the memory, wherein the first processor and the second processor access the region of the pool of the memory, issuing a free operation for release of the allocated region of the pool of the memory by a second process executed on a second processor, and releasing, by the first processor, the allocated region of the pool of the memory as indicated in the free operation, wherein the region of the pool of the memory allocated by the first process and released by the second process is a same region of memory.

Abstract: There is provided a computer implemented method of allocation of memory, comprising: issuing an allocation operation for allocation of a region of a pool of a memory by a first process executed on a first processor, sending a message to a second processor indicating the allocation of the region of the pool of the memory, wherein the first processor and the second processor access the region of the pool of the memory, issuing a free operation for release of the allocated region of the pool of the memory by a second process executed on a second processor, and releasing, by the first processor, the allocated region of the pool of the memory as indicated in the free operation, wherein the region of the pool of the memory allocated by the first process and released by the second process is a same region of memory.

Abstract: There is provided a device for allocation of memory configured for: in response to a request for allocation of a region of a pool of a memory by a process being executed by a processor, a memory allocator is configured to perform in a single atomic operation: read a data structure indicating a state of allocation of the pool, check the data structure for a condition, update the data structure according to an outcome of the check, and return an address of the allocated region of the memory.

Abstract: A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.

Abstract: A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.

Abstract: A method for executing a software program, comprising: identifying in a program a plurality of host threads, each for performing some of a plurality of parallel sub-tasks of a task; and for each of the host threads: generating device threads, each associated with the host thread, each for one of the parallel tasks associated thereof; generating a parent thread associated with the host thread for communicating with the device threads; configuring a host processing circuitry to execute the parent thread; and configuring at least one other processing circuitry to execute in parallel the device threads while the host processing circuitry executes the parent thread; and for at least one of the host threads: receiving by the parent thread a value from the at least one other processing circuitry, the value generated when executing at least one of the device threads associated with the at least one host thread.

Abstract: A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.