Patents by Inventor Dan Tamir

Dan Tamir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8307196
    Abstract: A method for operating a data processing system is provided. The method includes providing a first operand stored in a first register, providing a second operand stored in the register, providing a third operand stored in the register. The method further includes executing a first instruction, where executing the first instruction comprises: (1) retrieving the first operand, the second operand, and the third operand from the first register; (2) performing an operation using the first operand, the second operand, and the third operand to generate a bit exact result.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: November 6, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Imran Ahmed, Dan Tamir
  • Publication number: 20110227241
    Abstract: A slip-form machine (220) for laying of a second concrete slab (120) of a sleeperless rail-bed including a locomotion mechanism (222, 232) adapted to provide axial translation of the machine along a first slab (110); a slip-form (370) adapted to receive concrete exiting a discharge port (336) via a rearward exit (340) and form an uncured second concrete slab (120) during the axial translation; and a height adjustment mechanism (360) operable to adjust a height of a cover (350) of a forward exit (338) with respect to the first concrete slab (110).
    Type: Application
    Filed: July 8, 2009
    Publication date: September 22, 2011
    Applicant: ASHTROM GROUP LTD.
    Inventors: Shachar Nave, Dan Tamir
  • Publication number: 20070239968
    Abstract: A method for operating a data processing system is provided. The method includes providing a first operand stored in a first register, providing a second operand stored in the register, providing a third operand stored in the register. The method further includes executing a first instruction, where executing the first instruction comprises: (1) retrieving the first operand, the second operand, and the third operand from the first register; (2) performing an operation using the first operand, the second operand, and the third operand to generate a bit exact result.
    Type: Application
    Filed: April 5, 2006
    Publication date: October 11, 2007
    Inventors: William Moyer, Imran Ahmed, Dan Tamir
  • Patent number: 5884089
    Abstract: A parallel computer processor that performs L1 norm calculations includes a plurality of processing elements and a data pipeline which couples the processing elements. The data vectors for which the L1 norm is to be calculated are stored in storage lines of a cache memory. In operation each processing element accesses data in its private storage column in the cache memory and calculates a term signal. The term signals are added to form the resulting L1 norm.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: March 16, 1999
    Assignee: Motorola, Inc.
    Inventors: Effi Orian, Yaron Ben-Arie, Dan Tamir, Shao-Wei Pan